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參數(shù)資料
| 型號(hào)： | SC1100UFH-266 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Geode⑩ Information Appliance On a Chip |
| 中文描述： | Geode⑩信息家電在一個(gè)芯片 |
| 文件頁(yè)數(shù)： | 191/348頁(yè) |
| 文件大小： | 2063K |
| 代理商： | SC1100UFH-266 |
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Revision 1.1
191
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G
Core Logic Module
(Continued)
Note:
This register configures the Core Logic module to support a 3V Suspend mode. Setting bit 0 causes the SUSP_3V signal to
assert after the appropriate conditions, stopping the system clocks. A delay of 0-15 msec is programmable (bits [7:4]) to allow
for a delay for the clock chip and CPU PLL to stabilize when an event Resumes the system.
A write to the CPU Suspend Command register (F0 Index AEh) with bit 0 written as:
0: Internal SUSP#/SUSPA# handshake occurs. The GX1 module is put into a low-power state, and the system clocks are not
stopped. When a break/resume event occurs, it releases the CPU halt condition.
1: Internal SUSP#/SUSPA# handshake occurs and the SUSP_3V signal is asserted, thus invoking a full system Suspend (both
GX1 module and system clocks are stopped). When a break event occurs, the SUSP_3V signal is deasserted, the PLL delay
programmed in bits [7:4] are invoked which allows the clock chip and GX1 module PLL to stabilize before deasserting the inter-
nal SUSP# signal.
Index BDh-BFh
Reserved
Reset Value: 00h
Index C0h-C3h
User Defined Device 1 Base Address Register (R/W)
Reset Value: 00000000h
31:0
User Defined Device 1 Base Address.
This 32-bit register supports power management (Trap and Idle timer resources)
for a PCMCIA slot or some other device in the system. The value in this register is used as the address comparator for the
device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CCh).
The Core Logic module cannot snoop addresses on the Fast-PCI bus unless it actually claims the cycle. Therefore, Traps
and Idle timers cannot support power management of devices on the Fast-PCI bus.
Index C4h-C7h
User Defined Device 2 Base Address Register (R/W)
Reset Value: 00000000h
31:0
User Defined Device 2 Base Address.
This 32-bit register supports power management (Trap and Idle timer resources)
for a PCMCIA slot or some other device in the system. The value in this register is used as the address comparator for the
device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CDh).
The Core Logic module cannot snoop addresses on the Fast-PCI bus unless it actually claims the cycle. Therefore, Traps
and Idle timers cannot support power management of devices on the Fast-PCI bus.
Index C8h-CBh
User Defined Device 3 Base Address Register (R/W)
Reset Value: 00000000h
31:0
User Defined Device 3 Base Address.
This 32-bit register supports power management (Trap and Idle timer resources)
for a PCMCIA slot or some other device in the system. The value in this register is used as the address comparator for the
device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CEh).
The Core Logic module cannot snoop addresses on the Fast-PCI bus unless the it actually claims the cycle. Therefore,
Traps and Idle timers cannot support power management of devices on the Fast-PCI bus.
Index CCh
User Defined Device 1 Control Register (R/W)
Reset Value: 00h
7
Memory or I/O Mapped.
Determines how User Defined Device 1 is mapped.
0: I/O.
1: Memory.
Mask.
If bit 7 = 0 (I/O):
Bit 6
0: Disable write cycle tracking.
1: Enable write cycle tracking.
Bit 5
0: Disable read cycle tracking.
1: Enable read cycle tracking.
Bits [4:0] Mask for address bits A[4:0].
If bit 7 = 1 (Memory):
Bits [6:0] Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) A[8:0] are ignored.
Note:
A "1" in a mask bit means that the address bit is ignored for comparison.
6:0
Index CDh
User Defined Device 2 Control Register (R/W)
Reset Value: 00h
7
Memory or I/O Mapped.
Determines how User Defined Device 2 is mapped.
0: I/O
1: Memory
Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SC1100UFH-300 | Geode⑩ Information Appliance On a Chip |
| SC11372 | MOBILE RADIO ANALOG PROCESSOR |
| SC11372CQ | MOBILE RADIO ANALOG PROCESSOR |
| SC140 | High-Performance Fix-Point DSP Core(高性能定點(diǎn)型數(shù)字信號(hào)處理器內(nèi)核) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC1100UFH-266 B1 | 制造商:Advanced Micro Devices 功能描述:I3O IC OPN |
| SC1100UFH-300 | 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:Geode⑩ Information Appliance On a Chip |
| SC1101 | 制造商:SEMTECH 制造商全稱(chēng):Semtech Corporation 功能描述:VOLTAGE MODE PWM CONTROLLER |
| SC1101_05 | 制造商:SEMTECH 制造商全稱(chēng):Semtech Corporation 功能描述:Asynchronous Voltage Mode PWM Controller |
| SC11014 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:300 / 1200 Bit Per Second Modem |
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