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| 型號(hào)： | SC1100UFH-266 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Geode⑩ Information Appliance On a Chip |
| 中文描述： | Geode⑩信息家電在一個(gè)芯片 |
| 文件頁(yè)數(shù)： | 119/348頁(yè) |
| 文件大?。?/td> | 2063K |
| 代理商： | SC1100UFH-266 |
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Revision 1.1
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G
Core Logic Module
(Continued)
5.2.3
The Core Logic module integrates a PCI bus mastering,
ATA-4 compatible IDE controller. This controller supports
UltraDMA, Multiword DMA and Programmed I/O (PIO)
modes. Two devices are supported on the IDE controller.
The data-transfer speed for each device can be indepen-
dently programmed. This allows high-speed IDE peripher-
als to coexist on the same channel as lower speed devices.
IDE Controller
The Core Logic module supports two IDE channels, a pri-
mary channel and a secondary channel.
The IDE interface provides a variety of features to optimize
system performance, including 32-bit disk access, post
write buffers, bus master, Multiword DMA, look-ahead read
buffer, and prefetch mechanism for each channel respec-
tively.
The IDE interface timing is completely programmable. Tim-
ing control covers the command active and recover pulse
widths, and command block register accesses. The IDE
data-transfer speed for each device on each channel can
be independently programmed allowing high-speed IDE
peripherals to coexist on the same channel as older, com-
patible devices.
The Core Logic module also provides a software accessi-
ble buffered reset signal to the IDE drive, F0 Index
44h[3:2]. The IDE_RST# signal (ball AD6) is driven low
during reset to the Core Logic module and can be driven
low or high as needed for device-power-off conditions.
5.2.3.1
Registers for configuring Channels 0 and 1 are located in
the PCI register space designated as Function 2 (F2 Index
40h-5Ch). Table 5-35 on page 225 provides the bit formats
for these registers. The IDE bus master configuration regis-
ters are accessed via F2 Index 20h which is Base Address
Register 4 in Function 2 (F2BAR4). See Table 5-36 on
page 229 for register/bit formats.
IDE Configuration Registers
The following subsections discuss Core Logic opera-
tional/programming details concerning PIO, Bus Master,
and UltraDMA/33 modes.
5.2.3.2
The IDE data port transaction latency consists of address
latency, asserted latency and recovery latency. Address
latency occurs when a PCI master cycle targeting the IDE
data port is decoded, and the IDE_ADDR[2:0] and
IDE_CS# lines are not set up. Address latency provides the
setup time for the IDE_ADDR[2:0] and IDE_CS# lines prior
to IDE_IOR# and IDE_IOW#.
PIO Mode
Asserted latency consists of the I/O command strobe
assertion length and recovery time. Recovery time is pro-
vided so that transactions may occur back-to-back on the
IDE interface without violating minimum cycle periods for
the IDE interface.
If IDE_IORDY is asserted when the initial sample point is
reached, no wait states are added to the command strobe
assertion length. If IDE_IORDY is negated when the initial
sample point is reached, additional wait states are added.
Recovery latency occurs after the IDE data port transac-
tions have completed. It provides hold time on the
IDE_ADDR[2:0] and IDE_CS# lines with respect to the
read and write strobes (IDE_IOR# and IDE_IOW#).
The PIO portion of the IDE registers is enabled through:
Channel 0 Drive 0 Programmed I/O Register
(F2 Index 40h)
Channel 0 Drive 1 Programmed I/O Register
(F2 Index 48h)
Channel 1 Drive 0 Programmed I/O Register
(F2 Index 50h)
Channel 1 Drive 1 Programmed I/O Register
(F2 Index 58h)
The IDE channels and devices can be individually pro-
grammed to select the proper address setup time, asserted
time, and recovery time.
The bit formats for these registers are shown inTable 5-36
on page 229. Note that there are different bit formats for
each of the PIO programming registers depending on the
operating format selected: Format 0 or Format 1:
F2 Index 44h[31] (Channel 0 Drive 0 — DMA Control
Register) sets the format of the PIO register.
— If bit 31 = 0, Format 0 is used and it selects the
slowest PIO mode (bits [19:16]) per channel for
commands.
— If bit 31 = 1, Format 1 is used and it allows indepen-
dent control of command and data.
Also listed in the bit formats are recommended values for
the different PIO modes. Note that these are only recom-
mended settings and are not 100% tested.
5.2.3.3
Two IDE bus masters are provided to perform the data
transfers for the primary and secondary channels. The IDE
controller of the Core Logic module off-loads the CPU and
improves system performance in multitasking environ-
ments.
Bus Master Mode
The bus master mode programming interface is an exten-
sion of the standard IDE programming model. This means
that devices can always be dealt with using the standard
IDE programming model, with the master mode functional-
ity used when the appropriate driver and devices are
present. Master operation is designed to work with any IDE
device that supports DMA transfers on the IDE bus.
Devices that work in PIO mode can only use the standard
IDE programming model.
The IDE bus masters use a simple scatter/gather mecha-
nism allowing large transfer blocks to be scattered to or
gathered from memory. This cuts down on the number of
interrupts to and interactions with the CPU.
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