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參數(shù)資料
| 型號： | SC-KIT-TBX |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 5/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | TIMERBLOX SAMPLE KIT |
| 設(shè)計(jì)資源： | TimerBlox Designer |
| 特色產(chǎn)品： | TimerBlox? |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TimerBlox® |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘振蕩器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | LTC6990，LTC6991，LTC6992-1，LTC6993-2，LTC6994-1 |
| 已供物品： | 裸板，樣品 IC |
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LTC6990
13
6990fc
For more information www.linear.com/LTC6990
OPERATION
Changing DIVCODE After Start-Up
Following start-up, the A/D converter will continue
monitoring VDIV for changes. Changes to DIVCODE will
be recognized slowly, as the LTC6990 places a priority on
eliminating any “wandering” in the DIVCODE. The typical
delay depends on the difference between the old and
new DIVCODE settings and is proportional to the master
oscillator period.
tDIVCODE =16 (DIVCODE + 6) tMASTER
A change in DIVCODE will not be recognized until it is
stable, and will not pass through intermediate codes. A
digital filter is used to guarantee the DIVCODE has settled
to a new value before making changes to the output. Then
the output will make a clean (glitchless) transition to the
new divider setting.
Start-Up Time
When power is first applied to the LTC6990 the power-on
reset (POR) circuit will initiate the start-up time, tSTART.
The OUT pin is floated (high-impedance) during this time.
The typical value for tSTART ranges from 0.5ms to 8ms
depending on the master oscillator frequency (indepen-
dent of NDIV):
tSTART(TYP) = 500 tMASTER
The start-up time may be longer if the supply or DIV
pin voltages are not stable. For this reason, it is recom-
mended to minimize the capacitance on the DIV pin so it
will properly track V+.
Figure 5. DIVCODE Change from 5 to 2
Figure 6. Typical Start-Up
100s/DIV
6990 F05
DIV
1V/DIV
OUT
1V/DIV
V+ = 3.3V
RSET = 200k
576s
100s/DIV
6990 F06
V+
1V/DIV
OUT
1V/DIV
V+ = 2.5V
DIVCODE = 4
RSET = 50k
OUTPUT CONNECTED
TO 1.25V THROUGH 25k
TO SHOW Hi-Z
470s
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