For more information www.linear.com/LTC6990 OPERATION The LTC6990 is built around a m" />
參數(shù)資料
型號(hào)： SC-KIT-TBX
廠商： Linear Technology
文件頁(yè)數(shù)： 2/30頁(yè)
文件大?。?/td> 0K
描述： TIMERBLOX SAMPLE KIT
設(shè)計(jì)資源： TimerBlox Designer
特色產(chǎn)品： TimerBlox?
標(biāo)準(zhǔn)包裝： 1
系列： TimerBlox®
主要目的： 計(jì)時(shí)，時(shí)鐘振蕩器
嵌入式： 否
已用 IC / 零件： LTC6990，LTC6991，LTC6992-1，LTC6993-2，LTC6994-1
已供物品： 裸板，樣品 IC
LTC6990
10
6990fc
For more information www.linear.com/LTC6990
OPERATION
The LTC6990 is built around a master oscillator with a
1MHz maximum frequency. The oscillator is controlled
by the SET pin current (ISET) and voltage (VSET), with a
1MHz 50k conversion factor that is accurate to ±0.8%
under typical conditions.
fMASTER =
1
tMASTER
= 1MHz 50k
ISET
VSET
A feedback loop maintains VSET at 1V ±30mV, leaving ISET
as the primary means of controlling the output frequency.
The simplest way to generate ISET is to connect a resistor
(RSET) between SET and GND, such that ISET = VSET/RSET.
The master oscillator equation reduces to:
fMASTER =
1
tMASTER
=
1MHz 50k
RSET
From this equation it is clear that VSET drift will not affect
the output frequency when using a single program resis-
tor (RSET). Error sources are limited to RSET tolerance and
the inherent frequency accuracy fOUT of the LTC6990.
RSET values between 50k and 800k (equivalent to ISET
between 1.25A and 20A) produce the best results,
although RSET may be reduced to 25k (ISET = 40A) with
reduced accuracy.
The LTC6990 includes a programmable frequency divider
which can further divide the frequency by 1, 2, 4, 8, 16,
32, 64 or 128 before driving the OUT pin. The divider ratio
NDIV is set by a resistor divider attached to the DIV pin.
fOUT =
1
tOUT
=
1MHz 50k
NDIV
ISET
VSET
With RSET in place of VSET/ISET the equation reduces to:
fOUT =
1
tOUT
=
1MHz 50k
NDIV RSET
DIVCODE
The DIV pin connects to an internal, V+ referenced 4-bit
A/D converter that monitors the DIV pin voltage (VDIV) to
determine the DIVCODE value. DIVCODE programs two
settings on the LTC6990:
1. DIVCODE determines the output frequency divider
setting, NDIV.
2. DIVCODE determines the state of the output when
disabled, via the Hi-Z bit.
VDIV may be generated by a resistor divider between V+
and GND as shown in Figure 1.
Figure 1. Simple Technique for Setting DIVCODE
6990 F01
LTC6990
V+
DIV
GND
R1
R2
2.25V TO 5.5V
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