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型號(hào)：	SC-80C32E-30/883
廠商：	ATMEL CORP
元件分類：	微控制器/微處理器
英文描述：	8-BIT, 30 MHz, MICROCONTROLLER, CDIP40
封裝：	SIDE BRAZED, DIP-40
文件頁(yè)數(shù)：	288/1021頁(yè)
文件大小：	15196K
代理商：	SC-80C32E-30/883

32072H–AVR32–10/2012

AT32UC3A3

Write the starting source address in the SARx register for channel x.

The values in the LLI.SARx register locations of each of the Linked List Items (LLIs) setup up in

memory, although fetched during a LLI fetch, are not used.

Write the channel configuration information into the CFGx register for channel x.

Designate the handshaking interface type (hardware or software) for the source

and destination peripherals. This is not required for memory. This step requires pro-

gramming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’

activates the hardware handshaking interface to handle source/destination

requests for the specific channel. Writing a ‘1’ activates the software handshaking

interface source/destination requests.

If the hardware handshaking interface is activated for the source or destination

peripheral, assign handshaking interface to the source and destination peripheral.

This requires programming the SRC_PER and DEST_PER bits, respectively.

Make sure that the LLI.CTLx register locations of all LLIs in memory (except the last)

are set as shown in Row 7 of Table 19-1 on page 327 while the LLI.CTLx register of the

last Linked List item must be set as described in Row 1 or Row 5 of Table 19-1 on page

327. Figure 19-7 on page 326 shows a Linked List example with two list items.

Make sure that the LLI.LLPx register locations of all LLIs in memory (except the last)

are non-zero and point to the next Linked List Item.

Make sure that the LLI.DARx register location of all LLIs in memory point to the start

destination block address proceeding that LLI fetch.

Make sure that the LLI.CTLx.DONE field of the LLI.CTLx register locations of all LLIs in

memory is cleared.

Clear any pending interrupts on the channel from the previous DMA transfer by writing

to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran,

ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that

all interrupts have been cleared.

10. Program the CTLx, CFGx registers according to Row 7 as shown in Table 19-1 on page

11. Program the LLPx register with LLPx(0), the pointer to the first Linked List item.

12. Finally, enable the channel by writing a ‘1’ to the ChEnReg.CH_EN bit. The transfer is

performed. Make sure that bit 0 of the DmaCfgReg register is enabled.

13. The DMACA fetches the first LLI from the location pointed to by LLPx(0).

The LLI.SARx, LLI.DARx, LLI. LLPx and LLI.CTLx registers are fetched. The LLI.SARx register

although fetched is not used.

14. Source and destination request single and burst DMACA transactions to transfer the

block of data (assuming non-memory peripherals). DMACA acknowledges at the com-

pletion of every transaction (burst and single) in the block and carry out the block

15. Table 19-1 on page 327The DMACA reloads the SARx register from the initial value.

Hardware sets the block complete interrupt. The DMACA samples the row number as

shown in Table 19-1 on page 327. If the DMACA is in Row 1 or 5, then the DMA trans-

fer has completed. Hardware sets the transfer complete interrupt and disables the

channel. You can either respond to the Block Complete or Transfer Complete interrupts,

or poll for the Channel Enable (ChEnReg.CH_EN) bit until it is cleared by hardware, to

detect when the transfer is complete. If the DMACA is not in Row 1 or 5 as shown in

16. The DMA transfer proceeds as follows:

If interrupts are enabled (CTLx.INT_EN = 1) and the block complete interrupt is un-

masked (MaskBlock[x] = 1’b1, where x is the channel number) hardware sets the

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