- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄271848 > SB-36113VX-2C6N (DATA DEVICE CORP) SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DMA PDF資料下載
參數(shù)資料
| 型號： | SB-36113VX-2C6N |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DMA |
| 文件頁數(shù)： | 4/8頁 |
| 文件大小： | 139K |
| 代理商： | SB-36113VX-2C6N |
4
Data Device Corporation
www.ddc-web.com
SB-36110VX
H-01/06-0
Each channel's operating parameters are set by means of bits
28 to 30 which are read/write bits. Bit 30 determines the band-
width and bits 28 and 29 determine the resolution (See the
RDC-19222S Series data sheet).
The register space between offsets 0x30 and 0x3b is reserved
for testing purposes and their outputs are unspecified.
The control and status register is located at offset 0x3c.
Read/write bits 0 to 11 control the INH signals of the respective
channels and should be set before reading the channel and
cleared between reads. Bit 13 invokes the self test mode while
bits 14 and 15 control the DC signals applied to the COS and
SIN inputs when in the test mode (see Wrap-Around Self-Test
section below).
WRAP-AROUND SELF-TEST
Bits 15, 14 and 13 in the control register are used to place the
card into a self-test mode. This test mode is an intrusive test
(that is it interrupts the incoming data to the converters) and it is
operative on all channels simultaneously.
When Bit 13 is On (logic “1”), the card is placed into the self-test
mode. This disconnects the signal inputs from SIN/COS and
instead applies the DC test signals switched by control bits 14
and 15. The logic value of bits 14 and 15 determines the angle
read by the converters (see TABLE 4). Bit 14 controls the COS
input and bit 15 controls the SIN input.These signals are either
at the internal reference level (approximately 2 V) or at zero cor-
responding to the control bit state
PARAMETER
UNITS
TYPICAL
MAX./MIN.
Polarity
Voltage Range
V
4.0
Voltage Scaling
(resolution
dependent)
RPS/V
Tracking Rate
Typical (See TABLE 2A & 2B)
4
Scale Factor
Error
Scale Factor TC
Reversal Error
Linearity
Zero Offset
Zero Offset TC
Load
%
PPM/ deg C
%
% output
mV
V/ deg C
k Ohms
10
100
1
0.5
5
15
20 (max.)
200 (max.)
2 (max.)
1 (max.)
15 (max.)
30 (max.)
10 (min.)
TABLE 3. VELOCITY CHARACTERISTICS
INTRODUCTION
The SB-36110VX card contains up to 12 channels of
Synchro/Resolver-to-Digital converters sharing 4 sets of refer-
ence signals; each reference is allocated to three input channels.
Selection of reference configuration and other hardware operat-
ing characteristics is carried out by means of jumpers and resis-
tor network position.
Each channel and its associated operating control and BIT func-
tions are grouped together into a set of 32-bit (4-byte) read/limit-
ed-write registers occupying a total of 64 bytes of memory-
mapped address space. This register block is placed in the VME
address space by means of 3 eight-section DIP switches repre-
senting address lines 8 to 31. Control and status information is
held in a register located at the top of the address space
(address offset 0x3c). There are 3 unused register locations.
ACCESS MODES
The card can be operated in 16-, 24-, or 32-bit address modes.
Selection of the address mode is set by two jumpers, JP1 (3) and
JP1 (2) which disable address lines A24-31 and A16-31 respec-
tively and set the AM0-5 combination to which the card will
respond with the selected address line combination. Operation in
protected mode is possible and is invoked by using jumper
JP1 (1). When this jumper is connected, the processor can only
access the card when in supervisor mode; otherwise the card
can be accessed in either supervisor or user mode. See TABLE
5 for a summary of jumper connections.
REGISTER MODEL
Each of the first twelve registers, addressed at offsets 0x00,
0x04, and 0x2c, read and control one RDC channel. The Most
Significant Bit (MSB/bit 31) is the inverted BIT output from the
channel so that a returned negative value indicates an unstable
signal. The result of the conversion appears in the least signifi-
cant 16 bits of the register. These are all read-only bits.
BIT 15
BIT 14
BIT 13
ANGLE
TABLE 4. CONVERTER ANGLE READ
IN SELF-TEST MODE
X
0
Input
0
1
Invalid Angle
0
1
0 degrees
1
0
1
90 degrees
1
45 degrees
X = Don’t Care
The converter BIT for all converters will be on when in test mode.
BUILT IN TEST (BIT)
The BIT from each converter is returned as the Most Significant
Bit (MSB) of each 32-bit channel register. It should be noted that
the signal is inverted for convenience in software so that a logic
one indicates a tracking failure and returns a negative value in a
32-bit read. In addition, a read of the control register will also pro-
vide the BIT from all the converters with Bit 31 being the
logical OR of all the converter BIT’s output. This provides the
user with a simple way of testing the BIT during a read. The user
can do this by testing the read data to see if it is negative.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SD-14550DX-894 | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CQIP34 |
| SD-14551DX-312 | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CQIP34 |
| SD340-542 | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP26 |
| SD340-861 | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP26 |
| SD-14551DX-854 | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CQIP34 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SB36L-A | 制造商:GULFSEMI 制造商全稱:Gulf Semiconductor 功能描述:SURFACE MOUNT SCHOTTKY BARRIER RECTIFIER VOLTAGE: 60V CURRENT: 3.0A |
| SB370 | 制造商:EIC 制造商全稱:EIC discrete Semiconductors 功能描述:SCHOTTKY BARRIER RECTIFIER DIODES |
| SB370_08 | 制造商:DIODES 制造商全稱:Diodes Incorporated 功能描述:3.0A SCHOTTKY BARRIER RECTIFIER |
| SB370-B | 制造商:DIODES 制造商全稱:Diodes Incorporated 功能描述:3.0A SCHOTTKY BARRIER RECTIFIER |
| SB370S | 制造商:EIC 制造商全稱:EIC discrete Semiconductors 功能描述:SCHOTTKY BARRIER RECTIFIER DIODES |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。