參數(shù)資料
型號: SAK-TC1762-128F80HL
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 80 MHz, MICROCONTROLLER, PQFP176
封裝: PLASTIC, LQFP-176
文件頁數(shù): 114/114頁
文件大?。?/td> 852K
代理商: SAK-TC1762-128F80HL
TC1762
Electrical Parameters
Preliminary
Data Sheet
95
V1.0, 2008-04
4.3.5
Phase Locked Loop (PLL)
Section 4.3.5 provides the characteristics of the PLL parameters and its operation in the
TC1762.
Note: All PLL characteristics defined on this and the next page are verified by design
characterization.
Phase Locked Loop Operation
When PLL operation is enabled and configured, the PLL clock
f
VCO (and with it the CPU
clock
f
CPU) is constantly adjusted to the selected frequency. The relation between fVCO
and
f
SYS is defined by: fVCO =K × fCPU. The PLL causes a jitter of fCPU and affects the
clock outputs TRCLK and SYSCLK (P4.3) which are derived from the PLL clock
f
VCO.
There are two formulas that define the (absolute) approximate maximum value of jitter
D
P in ns dependent on the K-factor, the CPU clock frequency fCPU in MHz, and the
number
P of consecutive f
CPU clock periods.
(4.1)
(4.2)
K : K-Divider Value
P : Number of
f
CPU periods
D
P : Jitter in ns
f
CPU : CPU frequency in MHz
Table 4-13
PLL Parameters (Operating Conditions apply)
Parameter
Symbol
Limit Values
Unit
Min.
Max.
Accumulated jitter
D
P
VCO frequency range
f
VCO
400
500
MHz
500
600
MHz
600
700
MHz
PLL base frequency
1)
1) The CPU base frequency which is selected after reset is calculated by dividing the limit values by 16 (this is
the K factor after reset).
f
PLLBASE
140
320
MHz
150
400
MHz
200
480
MHz
PLL lock-in time
t
L
200
s
P
K
900
<
×
Dp ns
[]
5P
×
fcpu MHz
[]
-----------------------------
0 9
,
+
±
=
P
K
900
×
Dp ns
[]
4500
fcpu MHz
[] K
×
----------------------------------------
0 9
,
+
±
=
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