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參數(shù)資料
| 型號： | SAK-C505L |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-bit CMOS Microcontroller |
| 中文描述： | 8位CMOS微控制器 |
| 文件頁數(shù)： | 52/85頁 |
| 文件大?。?/td> | 487K |
| 代理商： | SAK-C505L |
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C505L
Data Sheet
50
06.99
Power Saving Modes
The C505L provides three basic power saving modes, the idle mode, the slow-down mode and the
software power down mode.
–
Idle mode
The CPU is gated off from the oscillator. All peripherals are still provided with the clock and
are able to work. Idle mode is entered by software and can be left by an interrupt or reset.
–
Slow down mode
The controller remains fully functional, but its normal clock frequency is internally divided by
32. This slows down all parts of the controller, the CPU and all peripherals, to 1/32 of their
normal operating frequency and also reduces power consumption.
–
Software power down modes:
Software power-down mode 1
, in which all the peripheral blocks and the CPU are stopped.
This mode is used to save contents of internal RAM, XRAM and SFRs with a very low standby
current.
Software power-down mode 2
, in which only the Real-time clock and LCD controller are
operating. In this mode, the CPU and the rest of the peripherals are stopped. The RC oscillator
and the on-chip oscillator are stopped, the real-time clock oscillator that operates with the
XTAL3 and XTAL4 pins is still running and the real-time count is maintained in this mode.
Software power-down mode 3
, in which only the real-time clock is operating. In this mode,
the clock input into the CPU, LCD controller and the rest of the peripherals are stopped. The
only difference between this mode and mode 2 is that the LCD controller is also stopped in
this mode.
In all the software power-down modes,
V
DD
can be reduced to minimize power consumption. In the
case of the software power-down mode 3,
V
DD
can be reduced to
3 V
(lower specification limit). It
must be ensured, however, that
V
DD
is not reduced before any of the power-down modes is invoked,
and that
V
DD
is restored to its normal operating level before leaving the power-down mode.
Any of these software power-down modes can be exited either by an active reset signal or by a
wake-up request. Using reset to leave power-down mode puts the microcontroller with its SFRs into
the reset state. Program execution then starts from the address 0000
H
. Using a wake-up request to
exit the power-down mode starts the RC oscillator and the on-chip oscillator and maintains the state
of the SFRs, which were frozen when power-down mode was entered.
When the C505L is in software power-down mode 1, a wake-up operation is possible only through
P3.2/INT0. There are two ways to use a wake-up request to exit power-down modes 2 and 3:
– Wake-up via P3.2/INT0 pin, or
– Wake-up via the real-time clock interrupt
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