參數(shù)資料
型號(hào)： SAK-C505L
廠商： INFINEON TECHNOLOGIES AG
元件分類： 8位微控制器
英文描述： 8-bit CMOS Microcontroller
中文描述： 8位CMOS微控制器
文件頁(yè)數(shù)： 22/85頁(yè)
文件大?。?/td> 487K
代理商： SAK-C505L
C505L
Data Sheet
20
06.99
Special Function Registers
The registers, except the program counter and the four general purpose register banks, reside in
the special function register area which consists of two portions: the standard special function
register area and the mapped special function register area. Some of the C505L’s SFRs (PCON1,
VR0, VR1 and VR2) are located in the mapped SFR area. For accessing the mapped SFR area, bit
RMAP in SFR SYSCON must be set. All other SFRs are located in the standard SFR area which is
accessed when RMAP is cleared (“0”).
The registers and data locations of the LCD Controller (LCD-SFRs) and the RTC (RTC-SFRs) are
located in the external data memory area at addresses F3DD
H
to F3EF
H
and F3F0
H
to F3FF
H
respectively.
Special Function Register SYSCON (Address B1
H
)
Reset Value: XX100X01
B
As long as bit RMAP is set, mapped SFR area can be accessed. This bit is not cleared automatically
by hardware. Thus, when non-mapped/mapped registers are to be accessed, the bit RMAP must
be cleared/set respectively by software.
All SFRs with addresses where address bits 0-2 are 0 (e.g. 80
H
, 88
H
, 90
H
, 98
H
,
…
, F8
H
, FF
H
) are
bit-addressable.
The 51 SFRs in the standard and mapped SFR area include pointers and registers that provide an
interface between the CPU and the other on-chip peripherals. The SFRs of the C505L are listed in
Table 2
and
Table 3
. In
Table 2
they are organized in groups which refer to the functional blocks of
the C505L. The LCD and RTC-SFRs are also included in
Table 2
.
Table 3
illustrates the contents
of the SFRs in numeric order of their addresses.
Table 4
lists the LCD and the RTC-SFRs in
numeric order of their addresses.
Bit
Function
RMAP
SFR map bit
RMAP = 0: Access to the non-mapped (standard) SFR area is enabled.
RMAP = 1: Access to the mapped SFR area is enabled.
–
Reserved bits for future use. Read by CPU returns undefined values.
The shaded bits are not described in this section.
_
_
EALE
RMAP
B1
H
SYSCON
Bit No.
7
6
5
4
3
2
1
0
MSB
LSB
_
_
XMAP1 XMAP0
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