- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374697 > SAF82525N (INFINEON TECHNOLOGIES AG) Data Communications ICs PDF資料下載
參數(shù)資料
| 型號(hào)： | SAF82525N |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | Data Communications ICs |
| 中文描述： | 數(shù)據(jù)通信集成電路 |
| 文件頁數(shù)： | 65/126頁 |
| 文件大?。?/td> | 730K |
| 代理商： | SAF82525N |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁當(dāng)前第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁
Semiconductor Group
65
SAB 82525
SAB 82526
SAF 82525
SAF 82526
This feature can be profitably used e.g. for:
user specific protocol variations
the application of character oriented protocols (e.g. BISYNC)
test purposes, line intentionally violation of HDLC protocol rules (e.g. wrong CRC)
FLAG insertion and deletion
CRC generation and checking
Bit-stuffing mechanism.
In order to enable fully transparent data transfer, RAC bit in MODE has to be reset and FF
H
has to be written to XAD1, XAD2 and RAH2.
Data transmission is always performed out of the transmit FIFO by directly shifting the contents
of the XFIFO via the serial transmit data pin (T
×
D). Transmission is initiated by setting
CMDR : XTF (08
H
); end of transmission is indicated by EXIR : EXE (40
H
).
In receive direction, the character currently assembled via the receive data line (R
×
D) is
available in the RAL1 register. Additionally, in extended transparent mode 1 (MODE: MDS1,
MDS0, ADM = 111), the received data is shifted into the RFIFO.
6
6.1 Fully Transparent Transmission and Reception
When programmed to the extended transparent mode via the MODE register (MDS1,
MDS0 = 11), each channel of the HSCX supports fully transparent data transmission and
reception without HDLC framing overhead, i.e. without
Special Functions
Character synchronization can be achieved either in
clock mode 1, with an external receive strobe input to A
×
CLK pin, or
clock mode 5, with a programmed time-slot and a frame synchronization signal input to
A
×
CLK.
Using clock mode 1 or 5 multiples of 8 bits received per time-slot.
6.2 Cyclic Transmission (Fully Transparent)
If the extended transparent mode is selected, the HSCX supports the continuous transmission
of the transmit FIFO’s contents.
After having written 1 to 32 bytes to the XFIFO, the command
XREP.XTF.XME
via the CMDR register (bit 7. . .0 = "00101010" = 2AH) forces the HSCX to repeatedly transmit
the data stored in the XFIFO via T
×
D pin.
The cyclic transmission continues until a reset command (CMDR : XRES) is issued, after
which continuous ’1’-s are transmitted.
Note:
In DMA-mode the command XREP, XTF has to be written to CMDR.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAF82526 | Data Communications ICs |
| SAF82526N | Data Communications ICs |
| SAB82525 | Data Communications ICs |
| SAB82525H | Data Communications ICs |
| SAF82532H-10 | ICs for Communications |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAF82525NV2.1 | 制造商:Infineon Technologies AG 功能描述: |
| SAF82525NV2.2 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T/E RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| SAF82525NV21 | 制造商:Infineon Technologies AG 功能描述:Communication Controller 44-Pin PLCC |
| SAF82525N-V21 | 功能描述:IC CONTROLLER 2-CH SER 44-PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| SAF82525V2.1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。