參數(shù)資料
型號： SAF-XC2264-72F66L
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 66 MHz, MICROCONTROLLER, PQFP100
封裝： 0.50 MM PITCH, GREEN, PLASTIC, LQFP-100
文件頁數(shù)： 15/116頁
文件大?。?/td> 1516K
代理商： SAF-XC2264-72F66L
XC2267 / XC2264
XC2000 Family Derivatives
Electrical Parameters
Data Sheet
109
V2.1, 2008-08
4.6.6
JTAG Interface Timing
The following parameters are applicable for communication through the JTAG debug
interface. The JTAG module is fully compliant with IEEE1149.1-2000.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Table 33
JTAG Interface Timing Parameters
(Operating Conditions apply)
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
Typ.
Max.
TCK clock period
t
1 SR
60
50
–
ns
–
TCK high time
t
2 SR
16
––ns
–
TCK low time
t
3 SR
16
––ns
–
TCK clock rise time
t
4 SR
–
–8ns
–
TCK clock fall time
t
5 SR
–
–8ns
–
TDI/TMS setup
to TCK rising edge
t
6 SR
6
––ns
–
TDI/TMS hold
after TCK rising edge
t
7 SR
6
––ns
–
TDO valid
after TCK falling edge1)
1) The falling edge on TCK is used to generate the TDO timing.
t
8 CC
–
30
ns
CL =50 pF
t
8 CC
10
––ns
CL =20 pF
TDO high imped. to valid
from TCK falling edge1)2)
2) The setup time for TDO is given implicitly by the TCK cycle time.
t
9 CC
–
30
ns
CL =50 pF
TDO valid to high imped.
from TCK falling edge1)
t
10 CC
–
30
ns
CL =50 pF
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