參數(shù)資料
型號： SAF-XC2264-72F66L
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 66 MHz, MICROCONTROLLER, PQFP100
封裝： 0.50 MM PITCH, GREEN, PLASTIC, LQFP-100
文件頁數(shù)： 11/116頁
文件大?。?/td> 1516K
代理商： SAF-XC2264-72F66L
XC2267 / XC2264
XC2000 Family Derivatives
Electrical Parameters
Data Sheet
106
V2.1, 2008-08
4.6.5
Synchronous Serial Interface Timing
The following parameters are applicable for a USIC channel operated in SSC mode.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Table 31
SSC Master/Slave Mode Timing for Upper Voltage Range
(Operating Conditions apply),
C
L = 50 pF
Parameter
Symbol
Values
Unit Note /
Test Co
ndition
Min.
Typ.
Max.
Master Mode Timing
Slave select output SELO active
to first SCLKOUT transmit edge
t
1 CC
0
–
1)
1) The maximum value further depends on the settings for the slave select output leading delay.
ns
2)
t
SYS =1/fSYS (= 12.5 ns @ 80 MHz)
Slave select output SELO inactive
after last SCLKOUT receive edge
t
2 CC
0.5
×
t
BIT
–
3)
3) The maximum value depends on the settings for the slave select output trailing delay and for the shift clock
output delay.
ns
Transmit data output valid time
t
3 CC
-6
–
13
ns
Receive data input setup time to
SCLKOUT receive edge
t
4 SR
31
–
ns
Data input DX0 hold time from
SCLKOUT receive edge
t
5 SR
-7
–
ns
Slave Mode Timing
Select input DX2 setup to first
clock input DX1 transmit edge
t
10 SR
7––ns
4)
4) These input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and
receive data input (bits DXnCR.DSEN = 0).
Select input DX2 hold after last
clock input DX1 receive edge
t
11 SR
5––ns
Data input DX0 setup time to
clock input DX1 receive edge
t
12 SR
7––ns
Data input DX0 hold time from
clock input DX1 receive edge
t
13 SR
5––ns
Data output DOUT valid time
t
14 CC
8
–
29
ns
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