參數(shù)資料
型號(hào): SAB9075H
廠商: NXP SEMICONDUCTORS
元件分類(lèi): 畫(huà)面疊加
英文描述: Circular Connector; No. of Contacts:10; Series:JT02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:12; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:12-98
中文描述: PICTURE-IN-PICTURE IC, PQFP100
封裝: PLASTIC, SOT-317, QFP-100
文件頁(yè)數(shù): 33/40頁(yè)
文件大?。?/td> 211K
代理商: SAB9075H
February 1995
33
Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
SAB9075H
Notes
1.
2.
Digital clocks are silent and analog bias current is zero.
The HUE and SAT DACs are based on a R2R ladder network as describe in the section “HUE and SAT DACs”. The
maximum output sample frequency is determined by the I
2
C-bus.
The input configuration of the ADCs is depicted in Fig.20. The minimum difference AV
refT
AV
refB
should be larger
than 1.0 V. The reference voltages can be calculated as follows:
5.0
5.0
3.
;
4.
The internal system frequencies are 1728 times the input frequency. For more detailed information about the clock
generation see section “PLLs and clock generation”.
TD
clamp
T
clamp
V
clampY
V
clampU
V
clampV
delay burstkey edge to clamping start
duration of clamping
clamping voltage level Y
0
2.33
V
s
0.5 V
T+B
0.5 V
T+B
μ
s
μ
s
V
AD
out
= 0H
AD
out
= 20H
AD
out
= 20H
clamping voltage level U
clamping voltage level V
V
V
Digital-to-analog converter
V
refT
Rin
ref
V
o(max)
R
L(min)
C
L(max)
Res
f
s
DNL
INL
α
cs
PSRR
top reference voltage (Y, U and V)
input resistance V
refT
to V
refB
maximum output voltage
minimum load resistance
maximum load capacitance
resolution
sample frequency rate
differential non-linearity
integral non-linearity
channel separation
power supply rejection ratio
note 3
note 3; 1 DAC
1.0
tbf
V
refB
10
0.5
1.0
tbf
tbf
1.5
1.0
50
7
27
40
40
2.0
tbf
V
refT
+0.5
+1.0
V
k
V
k
pF
bit
MHz
LSB
LSB
dB
dB
note 4
Digital-to-analog converter HUE/SAT
V
o
R
L(min)
C
L(max)
Res
DNL
INL
PSRR
output voltage
minimum load resistance
maximum load capacitance
resolution
differential non-linearity
integral non-linearity
power supply rejection ratio
V
SS
100
1.0
1.0
50
6
0
V
DD
+1.0
+1.0
V
k
pF
bit
LSB
LSB
dB
note 2
note 2
PLL and clock generation;
note 4
V
TOP
V
LOW
V
slice
f
PLL
TOP-level input voltage
LOW-level input voltage
slicing voltage level below TOP
input frequency
2.5
0.45
14750
1.0
15734
PV
DD
0.5
2.0
17250
V
V
V
Hz
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
refT
AV
DD
1.9
×
V
=
V
refB
AV
DD
0.4
-------
×
V
=
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