參數(shù)資料
型號(hào): SAB9075H
廠商: NXP SEMICONDUCTORS
元件分類: 畫面疊加
英文描述: Circular Connector; No. of Contacts:10; Series:JT02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:12; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:12-98
中文描述: PICTURE-IN-PICTURE IC, PQFP100
封裝: PLASTIC, SOT-317, QFP-100
文件頁(yè)數(shù): 26/40頁(yè)
文件大小: 211K
代理商: SAB9075H
February 1995
26
Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
SAB9075H
Table 17
Register A; decoder format register
Notes
1.
2.
MCOLPOL and SCOPOL invert the UV video data.
MVSPOL and SVSPOL determine the active edge of the V
sync
. If VSPOL is logic 0, the positive edge of the V
sync
will
be taken; if VSPOL is logic 1, the negative edge of the V
sync
will be taken.
MHSYNC and SHSYNC determine whether the H
sync
signal or the burstkey is used as internal horizontal
synchronization.
3.
BIT
MODE
RESULT
7
6
5
4
3
2
1
0
MCOLPOL
(1)
MVSPOL
(2)
MHSYNC
(3)
MFPOL
SCOLPOL
(1)
SVSPOL
(2)
SHSYNC
(3)
SFPOL
main-UV polarity; logic 0 = original; logic 1 = inverted
main-vertical sync polarity; logic 0 = positive pulse; logic 1 = negative pulse
main-horizontal sync selection; logic 0 = burst edge; logic 1 = H
sync
main-field polarity; inverts field identification window
sub-UV polarity; logic 0 = original; logic 1 = inverted
sub-vertical sync polarity; logic 0 = positive pulse; logic 1 = negative pulse
sub-horizontal sync selection; logic 0 = burst edge; logic 1 = H
sync
sub-field polarity, inverts field identification window
The exact timing of the V
sync
in relation to the H
sync
reference pulse is depicted in Fig.18. A field identification
window determines whether a V
sync
is being handled as a
1st field or a 2nd field. This field identification window can
be inverted by the FPOL bit. If FPOL is logic 0 and an
active edge of the V
sync
occurs when the F-ID signal is
logic 0, it will be regarded as the 1st field. If FPOL is logic 0
and an active edge of the V
sync
occurs when the F-ID
signal is logic 1, it will be regarded as the 2nd field. If FPOL
is logic 1 the 1st and 2nd field IDs are changed over.
Fig.18 V
sync
timing and field identification.
handbook, full pagewidth
MBE100
432
389
43
1st field
2nd field
field ID (internal)
(number of pixels)
Vsync
Vsync
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