參數(shù)資料
型號: SAB82525H
廠商: INFINEON TECHNOLOGIES AG
英文描述: Data Communications ICs
中文描述: 數(shù)據(jù)通信集成電路
文件頁數(shù): 101/126頁
文件大?。?/td> 730K
代理商: SAB82525H
Semiconductor Group
101
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Any state transition at the CTS input pin may cause an interrupt which is indicated in the
EXIR register (CSC bit). The actual state at the CTS pin can be determined reading the CTS
bit of the STAR register.
0 … disable
1 … enable
CIE … Clear To Send Interrupt Enable
When, the RFS interrupt (via EXIR) is enabled!
RIE … Receive Frame Start Interrupt Enable
Only valid if NRZ data encoding is selected. Data is transmitted and received inverted.
DIV … Data Inversion
Together with bits XCS2, XCS1 (RCS2, RCS1) in TSAX (TSAR) the clock shift relative to
the frame synchronization signal of the transmit (receive) time-slot can be adjusted.
A clock shift of 0 … 7 bits is programmable (clock mode 5 only!).
XCS0, RCS0 … Transmit/Receive Clock Shift, Bit 0
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