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參數資料
| 型號： | SAB-C167CS-4R33M |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | MN Series Basic Switch, Double Pole Double Throw Double Break Circuitry, 15 A at 480 Vac, Pin Plunger Actuator, 3,34 N - 5,56 N [12 oz - 20 oz] Operating Force, Gold Contacts, Quick Connect Termination Silver Contacts, Screw Termination CSA, UL |
| 中文描述： | 16位單片機 |
| 文件頁數： | 65/80頁 |
| 文件大?。?/td> | 1151K |
| 代理商： | SAB-C167CS-4R33M |
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C167CS-4R
C167CS-L
Data Sheet
61
V2.0, 2000-06
Sample time and conversion time of the C167CS’s A/D Converter are programmable.
Table 13
should be used to calculate the above timings.
The limit values for
f
BC
must not be exceeded when selecting ADCTC.
Converter Timing Example:
Assumptions:
Basic clock
Sample time
Conversion time
f
CPU
f
BC
t
S
t
C
= 25 MHz (i.e.
t
CPU
= 40 ns), ADCTC = ‘00’, ADSTC = ‘00’.
=
f
CPU
/4 = 6.25 MHz, i.e.
t
BC
= 160 ns.
=
t
BC
×
8 = 1280 ns.
=
t
S
+ 40
t
BC
+ 2
t
CPU
= (1280 + 6400 + 80) ns = 7.8
μ
s.
6)
During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal
resistance of the reference voltage source must allow the capacitance to reach its respective voltage level
within each conversion step. The maximum internal resistance results from the programmed conversion
timing.
7)
Not 100% tested, guaranteed by design and characterization.
8)
During the sample time the input capacitance
C
AIN
can be charged/discharged by the external source. The
internal resistance of the analog source must allow the capacitance to reach its final voltage level within
t
S
.
After the end of the sample time
t
S
, changes of the analog input voltage have no effect on the conversion result.
Values for the sample time
t
S
depend on programming and can be taken from
Table 13
.
Table 13
ADCON.15|14
(ADCTC)
00
01
10
11
A/D Converter Computation Table
A/D Converter
Basic Clock
f
BC
f
CPU
/4
f
CPU
/2
f
CPU
/16
f
CPU
/8
ADCON.13|12
(ADSTC)
00
01
10
11
Sample time
t
S
t
BC
×
8
t
BC
×
16
t
BC
×
32
t
BC
×
64
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