參數(shù)資料
型號： SAB-C167CS-4R33M
廠商： INFINEON TECHNOLOGIES AG
英文描述： MN Series Basic Switch, Double Pole Double Throw Double Break Circuitry, 15 A at 480 Vac, Pin Plunger Actuator, 3,34 N - 5,56 N [12 oz - 20 oz] Operating Force, Gold Contacts, Quick Connect Termination Silver Contacts, Screw Termination CSA, UL
中文描述： 16位單片機
文件頁數(shù)： 60/80頁
文件大?。?/td> 1151K
代理商： SAB-C167CS-4R33M
C167CS-4R
C167CS-L
Data Sheet
56
V2.0, 2000-06
P0.15-13 (P0H.7-5). Register RP0H can be loaded from the upper half of register
RSTCON under software control.
Table 10
associates the combinations of these three bits with the respective clock
generation mode.
Prescaler Operation
When prescaler operation is configured (CLKCFG=001
B
) the CPU clock is derived from
the internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of
f
CPU
is half the frequency of
f
OSC
and the high and low time of
f
CPU
(i.e.
the duration of an individual TCL) is defined by the period of the input clock
f
OSC
.
The timings listed in the AC Characteristics that refer to TCLs therefore can be
calculated using the period of
f
OSC
for any TCL.
Phase Locked Loop
When PLL operation is configured (via CLKCFG) the on-chip phase locked loop is
enabled and provides the CPU clock (see table above). The PLL multiplies the input
frequency by the factor
F
which is selected via the combination of pins P0.15-13 (i.e.
f
CPU
=
f
OSC
×
F
). With every
F
’th transition of
f
OSC
the PLL circuit synchronizes the CPU
clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock
frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of
f
CPU
is constantly adjusted so
it is locked to
f
OSC
. The slight variation causes a jitter of
f
CPU
which also effects the
duration of individual TCLs.
Table 10
CLKCFG
(RP0H.7-5)
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
C167CS Clock Generation Modes
CPU Frequency
f
CPU
=
f
OSC
×
F
f
OSC
×
4
f
OSC
×
3
f
OSC
×
2
f
OSC
×
5
f
OSC
×
1
f
OSC
×
1.5
f
OSC
/ 2
f
OSC
×
2.5
External Clock
Input Range
1)
2.5 to 8.25 MHz
3.33 to 11 MHz
5 to 16.5 MHz
2 to 6.6 MHz
1 to 33 MHz
6.66 to 22 MHz
2 to 66 MHz
4 to 13.2 MHz
1)
The external clock input range refers to a CPU clock range of 10 … 33 MHz.
2)
The maximum frequency depends on the duty cycle of the external clock signal.
Notes
Default configuration
–
–
–
Direct drive
2)
–
CPU clock via prescaler
–
相關PDF資料
PDF描述
SAB-C167CS-4RM MN Series Basic Switch, Double Pole Double Throw Double Break Circuitry, 15 A at 480 Vac, Pin Plunger Actuator, 1,95 N - 3,1 N [7 oz - 11 oz] Operating Force, Quick Connect Termination, Fine Silver Contacts, Screw Termination, CSA, UL
SAB-C167CS-LM 3MS1 QPL Series Military Thermostats
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