參數(shù)資料
型號: SAB-C165-LF HA
廠商: Infineon Technologies
文件頁數(shù): 44/77頁
文件大小: 0K
描述: IC MCU 16BIT TQFP-100-3
標(biāo)準(zhǔn)包裝: 1,400
系列: C16xx
核心處理器: C166
芯體尺寸: 16-位
速度: 20MHz
連通性: EBI/EMI,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 77
程序存儲器類型: ROMless
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 100-LQFP
包裝: 帶卷 (TR)
其它名稱: B165LFHAXP
C165LFHABXQMA1
SABC165LFHAX
SP000011595
SP000011596
C165
Data Sheet
45
V2.0, 2000-12
Memory Cycle Variables
The timing tables below use three variables which are derived from the BUSCONx
registers and represent the special characteristics of the programmed memory cycle.
The following table describes, how these variables are to be computed.
Note: Please respect the maximum operating frequency of the respective derivative.
AC Characteristics
Table 12
Memory Cycle Variables
Description
Symbol
Values
ALE Extension
tA
TCL
× <ALECTL>
Memory Cycle Time Waitstates
tC
2TCL
× (15 - <MCTC>)
Memory Tristate Time
tF
2TCL
× (1 - <MTTC>)
Multiplexed Bus (Standard Supply Voltage Range)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2
tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 25 MHz
Variable CPU Clock
1 / 2TCL = 1 to 25 MHz
Unit
min.
max.
min.
max.
ALE high time
t5
CC
10 +
tA
–TCL - 10
+
tA
–ns
Address setup to ALE
t6
CC
4 +
tA
–TCL - 16
+
tA
–ns
Address hold after ALE
t7
CC
10 +
tA
–TCL - 10
+
tA
–ns
ALE falling edge to RD,
WR (with RW-delay)
t8
CC
10 +
tA
–TCL - 10
+
tA
–ns
ALE falling edge to RD,
WR (no RW-delay)
t9
CC
- 10 +
tA
- 10 +
tA
–ns
Address float after RD,
WR (with RW-delay)
t10 CC –
6
–6ns
Address float after RD,
WR (no RW-delay)
t11 CC –
26
TCL + 6
ns
RD, WR low time
(with RW-delay)
t12 CC 30 + tC
2TCL - 10
+
tC
–ns
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