參數(shù)資料
型號: SAB-C165-LF HA
廠商: Infineon Technologies
文件頁數(shù): 11/77頁
文件大小: 0K
描述: IC MCU 16BIT TQFP-100-3
標(biāo)準(zhǔn)包裝: 1,400
系列: C16xx
核心處理器: C166
芯體尺寸: 16-位
速度: 20MHz
連通性: EBI/EMI,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 77
程序存儲器類型: ROMless
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 100-LQFP
包裝: 帶卷 (TR)
其它名稱: B165LFHAXP
C165LFHABXQMA1
SABC165LFHAX
SP000011595
SP000011596
C165
Data Sheet
15
V2.0, 2000-12
Central Processing Unit (CPU)
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic
and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a
separate multiply and divide unit, a bit-mask generator and a barrel shifter.
Based on these hardware provisions, most of the C165’s instructions can be executed
in just one machine cycle which requires 80 ns at 25 MHz CPU clock. For example, shift
and rotate instructions are always processed during one machine cycle independent of
the number of bits to be shifted. All multiple-cycle instructions have been optimized so
that they can be executed very fast as well: branches in 2 cycles, a 16
× 16 bit
multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. Another pipeline
optimization, the so-called ‘Jump Cache’, allows reducing the execution time of
repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
Figure 5
CPU Block Diagram
MCB02147
CPU
SP
STKOV
STKUN
Instr. Reg.
Instr. Ptr.
Exec. Unit
4-Stage
Pipeline
MDH
MDL
PSW
SYSCON
Context Ptr.
Mul/Div-HW
R15
R0
General
Purpose
Registers
Bit-Mask Gen
Barrel - Shifter
ALU
(16-bit)
Data Page Ptr.
Code Seg. Ptr.
Internal
RAM
R15
R0
ROM
16
32
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
ADDRSEL 4
ADDRSEL 3
ADDRSEL 2
ADDRSEL 1
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