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參數(shù)資料
| 型號： | SAA7384 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems |
| 中文描述： | 地面數(shù)字音頻解碼器為傳統(tǒng)載波鎖相環(huán)中頻系統(tǒng) |
| 文件頁數(shù)： | 13/40頁 |
| 文件大?。?/td> | 182K |
| 代理商： | SAA7384 |
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1996 Oct 24
13
Philips Semiconductors
Preliminary specification
Terrestrial digital sound decoder for
conventional intercarrier PLL-IF systems
SAA7284
I
2
C-bus slave receiver register map
Table 4
Slave receiver data byte
SUB-ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
000
001
010
011
100
M1/M2
EMAX7
EMIN7
C4OV
ASYS
DMSEL
EMAX6
EMIN6
MUTE
BG/I
SSWIT3
EMAX5
EMIN5
SILENCE
NICLEV
SSWIT2
EMAX4
EMIN4
DAIE
STLOCK
SSWIT1
EMAX3
EMIN3
FM3
PORT2
EMAX2
EMIN2
FM2
MUTEDEF
EMAX1
EMIN1
FM1
AMDIS
EMAX0
EMIN0
FM0
M1/M2
This bit selects either mono channel M1 or M2 to be the
output on the left and right channel dependent on the
transmitted control bits C1 and C2 indicating a mono
transmission and the value of bit DMSEL (see Table 5).
Power-on resets to logic 1.
DMSEL
DMSEL is the dual mono selection bit, for transmissions
consisting of two independent mono signals. Selection is
in conjunction with M1/M2 (see Table 5). Power on resets
to logic 0.
SSWIT1, SSWIT2
AND
SSWIT3
These bits control the analog switching, selecting between
the FM, external, and NICAM signals. With the NICAM
source the signals select whether the de-emphasis is
performed and what gain is applied after the filtering and
de-emphasis stage. The signal states and their meaning
are listed in Table 7. Power-on resets to 010 with PORA
pin HIGH, and to 011 with PORA pin LOW.
PORT2
PORT2 controls a bit out, providing direct access to a
dedicated output pin (PORT2) via the I
2
C-bus.
See Table 6. Power-on resets to logic 0.
MUTEDEF
This defines the operation of the user definable MUTE pin
orMUTE I
2
C-bus bit when it is pulled LOW externally or set
LOW in the I
2
C-bus respectively.
When this bit is HIGH, pulling the MUTE pin/I
2
C-bus bit
LOW will mute (set to zero) the digital data and switch the
output to the FM input, depending on relevant control bits
(see Table 8). When this bit is LOW, pulling the MUTE
pin/I
2
C-bus bit LOW will only mute the digital data under
the same conditions. Power-on resets to LOW.
AMDIS
This bit enables and disables the automatic mute function.
Power-on resets to enabled = LOW.
EMAX7
TO
EMAX0
This is the upper error limit register which defines the
number of errors in 128 ms period which will cause
automatic mute to switch IN. User definable, but power-on
resets to 50 (HEX).
EMIN7
TO
EMIN0
This is the lower error limit register which defines the
number of errors in 128 ms period which will cause
automatic mute to switch OUT. User definable, but
power-on resets to 14 (HEX).
C4OV
When set LOW this bit overrides the status of the
transmitted C4-bit when muting. When this bit is HIGH
muting takes place in accordance with EBU specification.
Power-on resets to HIGH when the PORA pin is held LOW
during power-up, and power-on resets to LOW when
PORA is HIGH.
MUTE
This reflects the function of the MUTEB pin. When this bit
is set LOW the external MUTEB pin is pulled LOW and the
action is dependent on the MUTEDEF bit (see Table 8).
Power-on resets to HIGH.
SILENCE
When set LOW this bit silences the outputs of the device
by switching the input of the audio switching buffers to
analog ground. When the PORM pin is held LOW at
power-on reset the silence bit is initialized to zero.
With PORM bit HIGH the silence bit is initialized HIGH.
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