參數(shù)資料
型號: SAA7370A
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: Digital servo processor and Compact Disc decoder CD7
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: 14 X 14 MM, 2.70 MM HEIGHT, PLASTIC, MS-022, SOT-393-1, QFP-64
文件頁數(shù): 8/60頁
文件大小: 248K
代理商: SAA7370A
1998 Feb 26
8
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder (CD7)
SAA7370A
7
FUNCTIONAL DESCRIPTION
7.1
Decoder part
7.1.1
P
RINCIPLE OPERATIONAL MODES OF THE DECODER
The decoding part can operate at different disc speeds,
from single-speed (n = 1) up to 8 times speed (n = 8).
The factor ‘n’ is called the overspeed factor. A simplified
data flow through the decoder part is illustrated in Fig.6.
7.1.2
D
ECODING SPEED AND CRYSTAL FREQUENCY
The SAA7370A is a multi-speed decoding device, with an
internal phase-locked loop (PLL) clock multiplier.
Depending on the crystal frequency used and the internal
clock settings (selectable via registers B and E), the
playback speeds shown in Table 1 are possible, where ‘n’
is the overspeed factor.
An internal clock multiplier is present, controlled by
SELPLL, and should only be used if an 8.4672 MHz or
16.9344 MHz crystal, ceramic resonator or external clock
is present.
7.1.3
L
OCK
-
TO
-
DISC MODE
For high speed CD-ROM applications, the SAA7370A has
a special mode, the lock-to-disc mode. This allows
Constant Angular Velocity (CAV) disc playback with
varying input data rates from the inside-to-outside of the
disc. In the lock-to-disc mode, the FIFO is blocked and the
decoder will adjust its output data rate to the disc speed.
Hence, the frequency of the I
2
S-bus (WCLK and SCLK)
clocks are dependent on the disc speed.
In the lock-to-disc mode there is a limit on the maximum
variation in disc speed that the SAA7370A will follow.
Disc speeds must always be within 25% to 100% range of
their nominal value. The lock-to-disc mode is
enabled/disabled by register E.
7.1.4
S
TANDBY MODES
The SAA7370A may be placed in two standby modes
selected by register B (it should be noted that the device
core is still active):
Standby 1: ‘CD-STOP’ mode. Most I/O functions are
switched off.
Standby 2: ‘CD-PAUSE’ mode. Audio output features
are switched off, but the motor loop, the motor output
and the subcode interfaces remain active. This is also
called a ‘Hot Pause’.
In the standby modes the various pins will have the
following values:
MOTO1 and MOTO2: put in high-impedance, PWM
mode (standby 1 and reset: operating in standby 2).
Put in high-impedance, PDM mode (standby 1 and
reset: operating in standby 2).
SCL, SDA, SILD and RAB: no interaction. Normal
operation continues.
SCLK, WCLK, DATA, EF, CL11 and DOBM: 3-state in
both standby modes. Normal operation continues after
reset.
CRIN, CROUT, CL16 and CL4: no interaction. Normal
operation continues.
V1, V2, V3, V4, V5, CFLG and C2FAIL: no interaction.
Normal operation continues.
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