參數(shù)資料
型號(hào)： SAA7370A
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： Digital servo processor and Compact Disc decoder CD7
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： 14 X 14 MM, 2.70 MM HEIGHT, PLASTIC, MS-022, SOT-393-1, QFP-64
文件頁(yè)數(shù)： 10/60頁(yè)
文件大?。?/td> 248K
代理商： SAA7370A
1998 Feb 26
10
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder (CD7)
SAA7370A
7.3
Data slicer and clock regenerator
The SAA7370A has an integrated slice level comparator
which can be clocked by the crystal frequency clock, or
8 times the crystal frequency clock (if SELPLL is set HIGH
while using an 8.4672 MHz crystal, and register 4 is set
to 0xxx). The slice level is controlled by an internal current
source applied to an external capacitor under the control
of the Digital Phase-Locked Loop (DPLL).
Regeneration of the bit clock is achieved with an internal
fully digital PLL. No external components are required and
the bit clock is not output. The PLL has two registers
(8 and 9) for selecting bandwidth and equalization.
For certain applications an offtrack input is necessary.
This is internally connected from the servo part (its polarity
can be changed by the foc_parm1 parameter), but may be
input via the V1 pin if selected by register C. If this flag is
HIGH, the SAA7370A will assume that its servo part is
following on the wrong track, and will flag all incoming HF
data as incorrect.
7.4
Demodulator
7.4.1
F
RAME SYNC PROTECTION
A double timing system is used to protect the demodulator
from erroneous sync patterns in the serial data.
The master counter is only reset if:
A sync coincidence detected; sync pattern occurs
588
±
1 EFM clocks after the previous sync pattern
A new sync pattern is detected within
±
6 EFM clocks of
its expected position.
The sync coincidence signal is also used to generate the
PLL lock signal, which is active HIGH after 1 sync
coincidence found, and reset LOW if during 61
consecutive frames no sync coincidence is found.
The PLL lock signal can be accessed via the SDA or
STATUS pins selected by register 2 and 7.
Also incorporated in the demodulator is a Run Length 2
(RL2) correction circuit. Every symbol detected as RL2 will
be pushed back to RL3. To do this, the phase error of both
edges of the RL2 symbol are compared and the correction
is executed at the side with the highest error probability.
7.4.2
EFM
DEMODULATION
The 14-bit EFM data and subcode words are decoded into
8-bit symbols.
Fig.5 Data slicer showing typical application components (for n = 4).
22 pF
100
nF
HFIN
HFREF
Iref
ISLICE
22 k
22 k
100 nF
1 nF
1 nF
HF
inputs
crystal
clock
D
Q
DPLL
1/2VDD
VSSA
VSS
VSSA
MBG397
VDD
100
μ
A
100
μ
A
相關(guān)PDF資料
PDF描述
SAA7370 Digital servo processor and Compact Disc decoder CD7
SAA7371 Digital servo processor and Compact Disc decoder CD7
SAA7371GP Digital servo processor and Compact Disc decoder CD7
SAA7372 Digital servo processor and Compact Disc decoder CD7
SAA7373 Digital servo processor and Compact Disc decoder CD7
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SAA7371 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital servo processor and Compact Disc decoder CD7
SAA7371GP 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital servo processor and Compact Disc decoder CD7
SAA7372 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital servo processor and Compact Disc decoder CD7
SAA7373 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital servo processor and Compact Disc decoder CD7
SAA7373GP 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital servo processor and Compact Disc decoder CD7
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