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參數(shù)資料
| 型號： | SAA7348GP |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | All Compact Disc Engine ACE |
| 中文描述： | 8-BIT, MROM, 35 MHz, MICROCONTROLLER, PQFP100 |
| 文件頁數(shù)： | 19/60頁 |
| 文件大小： | 205K |
| 代理商： | SAA7348GP |
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1997 Jul 11
19
Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
SAA7348GP
7.8
CD-ROM support
The principle difference between the ACE and its
predecessors with regard to CD-ROM support is the
provision of a separate serial data pin, which removes the
need for external components. The format can be I
2
S or
EIAJ.
7.8.1
S
ERIAL
CD-ROM
DATA INTERFACE
The serial data signal contains three components: WCLK
(word select), SCLK (serial clock) and DATA (serial data).
The polarity of WCLK and of the data can be inverted.
WCLK and SCLK are common with the audio serial data
output. The VALID signal is used to flag errors in either the
LSB or MSB of the 16-bit data word.
7.9
Reset
The RST pin on the SAA7348 is an active HIGH Schmitt
trigger. For a valid reset, the signal should be HIGH for a
period of 12 XTALI clock cycles, during which time the
power supply must be within specification on all power
supply pins. To ensure that the SAA7348 resets fully it is
necessary to do one of the following:
Connect SELPLL to DSDEN (rather than V
DD
). This
allows the internal clock multiplier to start immediately
after reset. Note that the internal clocks are not
guaranteed to operate at the correct frequencies for the
first 200
μ
s after reset. Note also that the operating
speed of the microcontroller is reduced in Idle mode
(and that baud rates change with the processor clock).
Connect SELPLL to an inverted reset signal.
The internal clock multiplier starts after reset, but during
Idle mode the microcontroller speed is normal.
7.10
External ROM support
Since the ACE incorporates an 80C51 core it can, like any
microcontroller, run a program from external ROM.
The EA pin should be tied to V
SS
in this case. For security
reasons, this pin is only sampled during reset, so a
program cannot be run partly from external ROM. Signal
relationships for external program execution are shown in
Fig.8. Timing specification can be found in Table 6.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA7350 | 20-BIT INPUT BITSTREAM CONVERSION DAC FOR DIGITAL AUDIO SYSTEMS |
| SAA7356HL | 1394 SBP-2 link layer controller |
| SAA7360GPB | Analog-to-Digital Converter， 18-Bit |
| SAA7366TD-T | Analog-to-Digital Converter， 18-Bit |
| SAA7360 | Bitstream conversion ADC for digital audio systems |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7350 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:20-BIT INPUT BITSTREAM CONVERSION DAC FOR DIGITAL AUDIO SYSTEMS |
| SAA7356HL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 SBP-2 link layer controller |
| SAA7360 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Bitstream conversion ADC for digital audio systems |
| SAA7360GP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Bitstream conversion ADC for digital audio systems |
| SAA7360GPB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 18-Bit |
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