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參數(shù)資料
| 型號： | SAA7348GP |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | All Compact Disc Engine ACE |
| 中文描述： | 8-BIT, MROM, 35 MHz, MICROCONTROLLER, PQFP100 |
| 文件頁數(shù)： | 17/60頁 |
| 文件大?。?/td> | 205K |
| 代理商： | SAA7348GP |
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1997 Jul 11
17
Philips Semiconductors
Preliminary specification
All Compact Disc Engine (ACE)
SAA7348GP
7.5
Digital output
The AES/EBU signal on pin DOBM is in accordance with
the format defined in “IEC 958” This signal is only
available in the decoder’s CLV modes if audio features are
enabled (not in QCLV modes). Three different modes can
be selected:
DOBM pin held LOW
Data taken before concealment, mute and fade (must
always be used for CD-ROM modes)
Data taken after concealment, mute and fade (can only
be used for audio modes).
7.5.1
F
ORMAT
The digital audio output consists of 32-bit words
(‘subframes’) transmitted in bi-phasemark code (two
transitions for a logic 1 and one transition for a logic 0).
Words are transmitted in blocks of 384.
Table 3
32-bit digital audio output format
Notes
1.
The sync word is formed in violation of the bi-phase rule and, therefore, does not contain any data. Its length is
equivalent to 4 data bits. The 3 different sync patterns indicate the following situations:
a) Sync B: word contains left sample (start of a block, 384 words).
b) Sync M: word contains left sample (no block start).
c) Sync W: word contains right sample.
Left and right samples are transmitted alternately.
Audio samples are flagged (bit 28 = 1) if an error was detected but could not be corrected. This flag remains the same
even if data is taken after concealment.
Subcode bits Q to W from the subcode section are transmitted via the user data bit. This data is asynchronous with
the block rate.
The channel status bit is the same for both left and right words. Therefore, a block of 384 words contains 192 channel
status bits. The category code is always CD. The bit assignment is shown in Table 4.
2.
3.
4.
5.
FUNCTION
BITS
DESCRIPTION
Sync
Auxiliary
Error flags
Audio sample
(2)
Validity flag
(3)
User data
(4)
Channel status
(5)
Parity bit
0 to 3
4 to 7
4
8 to 27
28
29
30
31
note 1
not used; normally zero
CFLG error and interpolation flags when selected by register A
first 4 bits not used (always zero); two’s complement; LSB = bit 12, MSB = bit 27
valid = logic 0
used for subcode data (Q to W)
control bits and category code
even parity for bits 4 to 30
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| SAA7350 | 20-BIT INPUT BITSTREAM CONVERSION DAC FOR DIGITAL AUDIO SYSTEMS |
| SAA7356HL | 1394 SBP-2 link layer controller |
| SAA7360GPB | Analog-to-Digital Converter， 18-Bit |
| SAA7366TD-T | Analog-to-Digital Converter， 18-Bit |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| SAA7350 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:20-BIT INPUT BITSTREAM CONVERSION DAC FOR DIGITAL AUDIO SYSTEMS |
| SAA7356HL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 SBP-2 link layer controller |
| SAA7360 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Bitstream conversion ADC for digital audio systems |
| SAA7360GP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Bitstream conversion ADC for digital audio systems |
| SAA7360GPB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 18-Bit |
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