參數(shù)資料
型號(hào)： SAA7346H
廠(chǎng)商： NXP SEMICONDUCTORS
元件分類(lèi)： 消費(fèi)家電
英文描述： Shock absorbing RAM addresser
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP44
封裝： 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44
文件頁(yè)數(shù)： 6/24頁(yè)
文件大?。?/td> 113K
代理商： SAA7346H
July 1994
6
Philips Semiconductors
Preliminary specification
Shock absorbing RAM addresser
SAA7346
the position of the subcode-sync to the audio data. This
signal determines the accuracy with which the SAA7346
sews audio data together after a shock. When the CD
decoder preforms a jump the NSF will be missed. The PLL
system will insert the missing pulse. The resulting signal is
the S_NSF which can be used as a time out for reading the
subcode from the decoder shown in Fig.4. The S_NSF is
available externally and the NSF flag can be read via the
serial microcontroller interface. The F6 flag indicates at
least one hold has occurred in the decoder’s error
corrector and interpolator. The shock processor uses this
signal to evaluate whether a shock has occurred.
handbook, full pagewidth
F1
F2
F3
F4
F5
F6
F7
F1
11.3
μ
s
45.4
μ
s
MGA370
CFLG
Fig.3 CFLG input timing diagram.
handbook, full pagewidth
Variable
NSF is set until read
by the microcontroller
0.37 ms
6.6 ms
S_NSF
NSF
MGB431
Fig.4 S_NSF output timing diagram; n = 2.
Shock processor
The shock processor determines whether a shock has
occurred by processing all the shock detectors. The
SAA7346 will enter shock mode and set SSD when the:
μ
Csd flag is set by the microcontroller in the command
register
OTD input is active while the jmp_bz flag is not set
RSB output is set while the e_rot_sd flag is set
NSF pulse is lost and the full flag is not read by the
microcontroller from the status register.
When the target position has been found the
microcontroller should set the PFB flag in the command
register. The SAA7346 will respond by clearing the SSD
flag and start refilling. If CFLG still indicates a hold, the
decoder is rolling out of its FIFO. RSB will be set which
sets SSD again thus the FIFO will not start refilling. The
microcontroller should jump one track back and look for
the correct target position again. When the motor speed is
stable and the decoder does not roll out of its FIFO, the
audio data will be glued together.
SSD will be reset whenever the microcontroller sets PFB
or the flush flags in the command register, or when the
FIFO empties while the echo flag is LOW. Note if the
microcontroller wants SSD to be clear for a while the shock
detectors should be inhibited.
FIFO controller and monitor
The SAA7346 uses a state machine to control and monitor
the conditions of the FIFO shown in Fig.5.
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