- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372115 > SAA7346H (NXP SEMICONDUCTORS) Shock absorbing RAM addresser PDF資料下載
參數(shù)資料
| 型號： | SAA7346H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Shock absorbing RAM addresser |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP44 |
| 封裝： | 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44 |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 113K |
| 代理商： | SAA7346H |
July 1994
5
Philips Semiconductors
Preliminary specification
Shock absorbing RAM addresser
SAA7346
D3 to D0
V
SS2
V
DD2
39 to 42
43
44
DRAM data bus inputs/outputs
supply ground 2
supply voltage 2
SYMBOL
PIN
DESCRIPTION
Fig.2 Pin configuration.
handbook, full pagewidth
MGB430
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
1
1
1
1
1
1
1
1
2
2
2
4
4
4
4
4
3
3
3
3
3
3
A8
A0
A7
A1
A6
A2
A5
A3
A4
CFLG
RCD2
KILL
SCLI
WCI
SDI
CONFIG
CLKIN
TMS
OTD
VSS1
VDD1
SAA7346
W
S
R
S
S
S
F
K
S
S
R
VD
VS
SSD
A
D
D
D
D
W
C
O
R
FUNCTIONAL DESCRIPTION
I
2
S input/output interfaces
The SAA7346 contains an asynchronous serial input and
a serial output interface. The serial operation of the
interfaces is under hardware control of the external
circuitry and uses the I
2
S protocol. The output presents a
continuous clock signal SCLO (typically 2.8224 MHz)
which is divided from the system clock, and a word select
signal WCO, typically 44.1 kHz (f
s
), which is used to
distinguish between right and left channels. When in
by-pass mode WCO and SCLO are the same as the input
interface signals WCI and SCLI, enabling data to pass
through the SAA7346. Since the serial input port is
asynchronous the device is independent of the CD
decoder clock speed and enables the word clock to vary
from 1.1
×
f
s
to 4
×
f
s
(typically 2
×
f
s
). This is a requirement
of any electronic shock absorbing system since the disc
must be rotating faster than usual to assure the FIFO is full
to absorb a shock. The falling edge of WCO indicates the
start of a new transfer. Data is exchanged over the
SDI and SDO pins. The SAA7346 is compatible with a
variety of DAC ICs.
New subcode frame regeneration
The SAA7346 has a digital phase-locked loop (PLL)
system which decodes the F1 and F6 flags, from the first
1-bit signal generated by the CD decoder correction flag
output shown in Fig.3. The F1 flag is the absolute time
sync signal of the New Subcode Frame (NSF). It relates
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA7348GP | All Compact Disc Engine ACE |
| SAA7350 | 20-BIT INPUT BITSTREAM CONVERSION DAC FOR DIGITAL AUDIO SYSTEMS |
| SAA7356HL | 1394 SBP-2 link layer controller |
| SAA7360GPB | Analog-to-Digital Converter， 18-Bit |
| SAA7366TD-T | Analog-to-Digital Converter， 18-Bit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7348GP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:All Compact Disc Engine ACE |
| SAA7350 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:20-BIT INPUT BITSTREAM CONVERSION DAC FOR DIGITAL AUDIO SYSTEMS |
| SAA7356HL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 SBP-2 link layer controller |
| SAA7360 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Bitstream conversion ADC for digital audio systems |
| SAA7360GP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Bitstream conversion ADC for digital audio systems |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。