參數(shù)資料
型號(hào)： SAA7206
廠商： NXP Semiconductors N.V.
英文描述： DVB compliant descrambler
中文描述： 兼容DVB解擾器
文件頁(yè)數(shù)： 12/52頁(yè)
文件大?。?/td> 193K
代理商： SAA7206
1996 Oct 09
12
Philips Semiconductors
Product specification
DVB compliant descrambler
SAA7206H
7.2
PES level descrambling
PES level descrambling is possible in accordance with the
recommendations of the DVB standard with the DVB
descrambler IC. The actual restrictions however, required
by the DVB descrambler IC, are less strict than to the
recommendations in the DVB standard. The restrictions
for PES level descrambling imposed by the IC are as
follows:
Scrambling shall only occur at one level (TS or PES) and
is not allowed to occur at both levels simultaneously
The complete PES header must be present in exactly
one TS packet. Consequently, the size of a PES packet
header shall not exceed 184 bytes
Only the PES packet data bytes (PES payload) are
descrambled
TS packets resulting from scrambling at PES level are
not chained and thus are independent. Consequently,
the internal descrambler algorithms (stream decipher
and block decipher) are initialized at the start of each
(PES scrambled) TS packet payload.
In order to be able to distinguish between sections and
PES packets, a PID for a PES scrambled packet is
indicated by programming the according ‘PIDi_is_pes’ bit
(see Table 10, address 0x0206) to logic 1. If the
payload_unit_start_indicator bit is set in the TS packet
header and the ‘PIDi_is_pes’ bit is set for a particular PID,
the PES scrambling control bits, which are present in the
PES header, are stored in the accessible ‘pes_sc_PIDi’
register (see Table 10, address 0x0208).
Descrambling at TS level always has priority over
descrambling at PES level. Consequently, PES level
descrambling is only possible when the
transport_scrambling_control bits in the TS header are
‘00’. In that situation the payload of the PES packets is
descrambled using the scrambling control bits of the
‘pes_sc_PIDi’ register.
Remark:
PID masking (for PID5) should not be combined
with PES level descrambling. Only one pair of PES
scrambling control bits per PID is stored in an Internal
register. Thus interleaving of PES messages, which can
occur in the situation of multiple PID selection, can give the
wrong descrambling result. As a consequence the
microcontroller must program the ‘PID5_is_pes’ bit
(see Table 10, address 0x0206) to logic 0 when multiple
PID selection is used.
7.3
Descrambler core
The descrambler core consists of three modules:
A PID filter which selects packets for descrambling
A control word bank containing 6 sets (odd and even) of
control words and a Default Control Word (DCW)
The super descrambler core with the implementation of
the stream decipherment and the block decipherment
algorithms.
The PID filter contains 6 registers which hold data in the
format indicated in Fig.7. Six individual PIDs are stored to
identify 6 packet streams. All bits of PID5 (see Table 10,
address 0x0205) can be masked with the ‘PID5_mask’
(see Table 10, address 0x209), to enable descrambling on
multiple PIDs. To disable a bit of PID5 with the
‘PID5_mask’ a logic 0 must be programmed. After a
power-on reset pulse all mask bits are preset to logic 1.
To each PID a 3-bit Control Word Pair Index pointer
(CWPI) is attached. A CWPI prescribes which control word
pair, consisting of odd and even control words, has to be
used to initialize the DVB descrambler for payloads of
packets with the associated PID. After a power-on reset all
CWPIs are set to ‘111’ to enable a correct initialization of
the conditional access system.
If two or more programmed PIDs match the PID of the TS
packet at the same time (while the CWPI value of the
programmed PIDs is not equal to ‘110’ or ‘111’), the
programmed PID with the lower index number has a higher
priority. However, the default control word, when enabled,
has the highest priority.
Thus, the built-in priority (HIGH-to-LOW transition) for the
programmed PIDs is; DCW, PID0, PID1, PID2, PID3, PID4
and PID5.
A 2-bit scrambling_control field is present in the TS packet
header and in the PES header (ts_sc1 and ts_sc0 and
pes_sc1 and pes_sc0 respectively). The bits in this
header field indicate whether the TS packet or PES
payload is scrambled or not. In addition, these bits also
indicate which control word (odd or even) of a control word
pair was used to initialize the DVB descrambler, as
indicated in Tables 2 and 3.
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