參數(shù)資料
型號(hào)： SAA7206
廠商： NXP Semiconductors N.V.
英文描述： DVB compliant descrambler
中文描述： 兼容DVB解擾器
文件頁(yè)數(shù)： 44/52頁(yè)
文件大?。?/td> 193K
代理商： SAA7206
1996 Oct 09
44
Philips Semiconductors
Product specification
DVB compliant descrambler
SAA7206H
Notes
1.
In the synchronous mode all input signals are referenced to the descrambler clock which is specified in the output
interface part. In the asynchronous mode all input signals are referenced to the MBCLK.
Data output is low impedance when both (DCS = 0) AND (R/W = 1). t
oL(Z)
is defined after the last change of both
signals which makes the data output low impedance. t
oH(Z)
is defined after the first change of both signals which
makes the data output high impedance.
2.
Output interface;
(see Fig.13)
C
o
C
L
T
cy(DCLK)
t
o(r)(DCLK)
t
o(f)(DCLK)
t
DCLKH
t
DCLKL
t
o(r)
t
o(f)
t
o(h)
t
o(d)
output capacitance
output load capacitance
output clock cycle time (DCLK)
output clock rise time
output clock fall time
output clock HIGH time
output clock LOW time
output rise time
output fall time
output hold time
output delay time
111
20
20
3
10
50
10
10
10
10
40
pF
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
L
= 5 pF
C
L
= 30 pF
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
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