
1996 Jul 03
5
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
CHROMA
V
DDA2
Y
V
SSA
CVBS
V
DDA3
IOA
49
50
51
52
53
54
55
O
I
O
O
I
I
analog output of the chrominance signal
analog supply voltage 2 for the DACs and output amplifiers
analog output of the luminance signal
analog ground for the DACs and output amplifiers
analog output of the CVBS signal
analog supply voltage 3 for the DACs and output amplifiers
current input for the output amplifiers (connected via a 15 k
resistor to
V
DDA
)
analog supply voltage 4 for the DACs and output amplifiers
Reset input, active LOW. After reset is applied, all outputs are in 3-state input
mode. The I
2
C-bus receiver waits for the start condition.
Data acknowledge output of the parallel MPU interface, active LOW,
otherwise high impedance.
If pin 68 (SEL_MPU) is HIGH, this is the read/write signal of the parallel MPU
interface. Otherwise it is the I
2
C-bus serial clock input.
If pin 68 (SEL_MPU) is HIGH, this is the address signal of the parallel MPU
interface. Otherwise it is the I
2
C-bus serial data input/output.
If pin 68 (SEL_MPU) is HIGH, this is the chip select signal of the parallel
MPU interface. Otherwise it is the I
2
C-bus slave address select pin. When
LOW slave address = 88H, when HIGH slave address = 8CH.
digital ground 7
Lower 4 bits of the data port; if pin 68 (SEL_MPU) is HIGH, the data bus of
the parallel MPU interface is used. If pin 68 is LOW, then the UV lines of the
video port are used.
digital supply voltage 3
Select MPU interface input; if it is HIGH, the parallel MPU interface is active,
if not the I
2
C-bus interface will be used.
V
DDA4
RES
56
57
I
I
DTACK
58
O
RWN/SCL
59
I
A0/SDA
60
I/O
CSN/SA
61
I
V
SSD7
DP0 to DP3
62
63 to 66
I/O
V
DDD3
SEL_MPU
67
68
I
I
SYMBOL
PIN
I/O
DESCRIPTION