
1996 Jul 03
22
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
Table 31
Subaddress 7A
Table 32
Subaddress 7B to 7D
Slave Transmitter
Table 33
Slave Transmitter (slave address 89H or 8DH)
Table 34
No subaddress
DATA BYTE
DESCRIPTION
FLC1
FLC0
0
0
field length control interlaced 312.5 lines/fields at 50 Hz, 262.5 lines/fields at 60 Hz
(reset default)
field length control non-interlaced 312 lines/fields at 50 Hz, 262 lines/fields at 60 Hz
field length control non-interlaced 313 lines/fields at 50 Hz, 262 lines/fields at 60 Hz
field length control non-interlaced 313 lines/fields at 50 Hz, 262 lines/fields at 60 Hz
0
1
1
1
0
1
DATA BYTE
DESCRIPTION
FAL
first active line = FAL + 4 for M systems; = FAL + 1 for other systems, measured in lines
FAL = 0 coincides with the first field synchronization pulse
last active line = LAL + 3 for M systems; = LAL for other systems, measured in lines
LAL = 0 coincides with the first field synchronization pulse
LAL
REGISTER
FUNCTION
SUBADDRESS
DATA BYTE
D7
D6
D5
D4
D3
D2
D1
D0
Status byte
VER2
VER1
VER0
CCRDO
CCRDE
FSQ2
FSQ1
FSQ0
DATA BYTE
DESCRIPTION
VER
Version identification of the device. It will be changed with all versions of the IC that have different
programming models. Current version is 100 binary.
1 = closed caption bytes of the odd field have been encoded.
0 = the bit is reset after information has been written to the subaddresses 67 and 68. It is set
immediately after the data have been encoded.
1 = closed caption bytes of the even field have been encoded.
0 = the bit is reset after information has been written to the subaddresses 69 and 6A. It is set
immediately after the data have been encoded.
State of the internal field sequence counter.
Bit 0 (FSQ0) gives the odd/even information; odd = LOW, even = HIGH.
CCRDO
CCRDE
FSQ