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參數(shù)資料
| 型號： | SAA7183A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Digital Video Encoder EURO-DENC2 |
| 中文描述： | 數(shù)字視頻編碼器歐元，DENC2 |
| 文件頁數(shù)： | 38/45頁 |
| 文件大小： | 203K |
| 代理商： | SAA7183A |
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1996 Oct 02
38
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
Teletext timing
Time t
FD
is the time needed to interpolate input data TTX
and inserting it into the CVBS and Y output signal, such
that it appears at t
TTX
= 10.2
μ
s after the leading edge of
the horizontal synchronization pulse.
Time t
PD
is the pipeline delay time introduced by the
source that is gated by TTXRQ in order to deliver TTX
data.
Since the pulse representing the TTXRQ signal is fully
programmable in duration and rising/falling edges (TTXHS
and TTXHE), the TTX data is always inserted at the correct
position of 10.2
μ
s after the leading edge of outgoing
horizontal synchronization pulse.
Time t
TTXWin
is the internally used insertion window for
TTX data; it has a constant length that allows insertion of
360 teletext bits (maximum) at a text data rate of
6.9375 Mbits/s. The insertion window is not opened if the
control bit TTXEN is zero.
T
ELETEXT PROTOCOL
The frequency relationship between TTX bit clock and the
system clock LLC for 50 Hz field rate is given by the
relationship of line frequency multiples, which means
1728/444.
Thus 37 TTX bits correspond to 144 LLC clocks, each bit
has a duration of nearly 4 LLC clocks. The chip-internal
sequencer and variable phase interpolation filter
minimizes the phase jitter, and thus generates a
bandwidth limited signal, which is digital-to-analog
converted for the CVBS and Y outputs.
At the TTX input, bit duration scheme repeats after 37 TTX
bits or 144 LLC clocks. The protocol demands that TXX
bits 10, 19, 28 and 37 are carried by three LLC samples,
all others by four LLC samples. After a cycle of 37 TTX
bits, the next bits with three LLC samples are bits 47, 56,
65 and 74; this scheme holds for all succeeding cycles of
37 TTX bits, until 360 TTX bits (including 16 run-in bits)
are completed. For every additional line with TTX data, the
bit duration scheme starts in the same way.
Using appropriate programming, all suitable lines of the
odd field (TTXOVS and TTXOVE) plus all suitable lines of
the even field (TTXEVS and TTXEVE) can be used for
teletext insertion.
Fig.19 Teletext timing diagram.
handbook, full pagewidth
tTTXWin
tTTX
tPD
tFD
CVBS/Y
TTX
TTXRQ
textbit #:
1
2
3
4
5
6
7
8
9
10 11
4
3
4
4
3
4
1/LLC
1/LLC
12
13
14
15
16
17
18 19 20
21
22
23
24
MGB701
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PDF描述 |
|---|---|
| SAA7167 | YUV-to-RGB Digital-to-Analog Converter DAC |
| SAA7174 | Analog TV video and stereo decoder for computing and consumer applications in Europe |
| SAA7182A | Digital Video Encoder EURO-DENC2 |
| SAA7182 | Digital Video Encoder EURO-DENC |
| SAA7182AWP | Digital Video Encoder EURO-DENC2 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7183AWP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Encoder EURO-DENC2 |
| SAA7183WP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Encoder EURO-DENC |
| SAA7184 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Encoders DENC2-M6 |
| SAA7184WP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Encoders DENC2-M6 |
| SAA7185 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Encoder DENC2 |
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