2000 Mar 08
6
Philips Semiconductors
Product specification
Digital video encoder
SAA7128H; SAA7129H
6
PINNING
SYMBOL
PIN
TYPE
I
I
I
supply digital ground 1
supply digital supply voltage 1
I/O
raster control 1 for video port; this pin receives/provides a VS/FS/FSEQ signal
I/O
raster control 2 for video port; this pin provides an HS pulse of programmable length or
receives an HS pulse
I
double-speed 54 MHz MPEG port; it is an input for “ITU-R BT656”style multiplexed
C
B
-Y-C
R
data; data is sampled on the rising and falling clock edge; data sampled on the
rising edge is then sent to the encoding part of the device; data sampled on the falling
edge is sent to the RGB part of the device (or vice versa, depending on programming)
I
I
I
I
I
supply digital supply voltage 2
supply digital ground 2
I
real-time control input; if the LLC1 clock is provided by an SAA7111 or SAA7151B, RTCI
should be connected to the RTCO pin of the respective decoder to improve the signal
quality
supply sense input for I
2
C-bus voltage; connect to I
2
C-bus supply
I
select I
2
C-bus address; LOW selects slave address 88H, HIGH selects slave address
8CH
supply analog ground 1 for RED (C
R
), C (CVBS) and GREEN (Y) outputs
O
analog output of RED (C
R
) signal
O
analog output of chrominance (CVBS) signal
supply analog supply voltage 1 for RED (C
R
) and C (CVBS) outputs
O
analog output of GREEN (Y) signal
O
analog output of VBS (CVBS) signal
supply analog supply voltage 2 for VBS (CVBS) and GREEN (Y) outputs
O
analog output of BLUE (C
B
) signal
O
analog output of CVBS (CSYNC) signal
supply analog supply voltage 3 for BLUE (C
B
) and CVBS (CSYNC) outputs
supply analog ground 2 for VBS (CVBS), BLUE (C
B
) and CVBS (CSYNC) outputs
supply analog ground 3 for the DAC reference ladder and the oscillator
O
crystal oscillator output
I
crystal oscillator input; if the oscillator is not used, this pin should be connected to ground
supply analog supply voltage 4 for the DAC reference ladder and the oscillator
DESCRIPTION
RES
SP
AP
LLC1
V
SSD1
V
DDD1
RCV1
RCV2
1
2
3
4
5
6
7
8
reserved pin; do not connect
test pin; connected to digital ground for normal operation
test pin; connected to digital ground for normal operation
line-locked clock input; this is the 27 MHz master clock
MP7
MP6
MP5
MP4
MP3
MP2
MP1
MP0
V
DDD2
V
SSD2
RTCI
9
10
11
12
13
14
15
16
17
18
19
I
I
V
DD(I2C)
SA
20
21
V
SSA1
RED
C
V
DDA1
GREEN
VBS
V
DDA2
BLUE
CVBS
V
DDA3
V
SSA2
V
SSA3
XTALO
XTALI
V
DDA4
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36