參數(shù)資料
型號： SAA7126H
廠商： NXP SEMICONDUCTORS
元件分類： 顏色信號轉(zhuǎn)換
英文描述： Digital video encoder
中文描述： COLOR SIGNAL ENCODER, PQFP44
封裝： 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44
文件頁數(shù)： 19/40頁
文件大?。?/td> 155K
代理商： SAA7126H
1999 May 31
19
Philips Semiconductors
Product specification
Digital video encoder
SAA7126H; SAA7127H
Table 27
Subaddress 6BH
Table 28
Logic levels and function of SRCV1
Table 29
Subaddresses 6CH and 6DH
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
PRCV2
0
polarity of RCV2 as output is active HIGH, rising edge is taken when input, respectively;
default after reset
polarity of RCV2 as output is active LOW, falling edge is taken when input, respectively
pin RCV2 is switched to input; default after reset
pin RCV2 is switched to output
If ORCV2 = HIGH, pin RCV2 provides an HREF signal (horizontal reference pulse that is
defined by RCV2S and RCV2E, also during vertical blanking interval); default after reset.
If ORCV2 = LOW and bit SYMP = LOW, the signal input to RCV2 is used for horizontal
synchronization only (if TRCV2 = 1); default after reset.
If ORCV2 = HIGH, pin RCV2 provides a ‘composite-blanking-not’ signal, for example a
reference pulse that is defined by RCV2S and RCV2E, excluding vertical blanking interval,
which is defined by FAL and LAL. If ORCV2 = LOW and bit SYMP = LOW, the signal input
to RCV2 is used for horizontal synchronization (if TRCV2 = 1) and as an internal blanking
signal.
polarity of RCV1 as output is active HIGH, rising edge is taken when input; default after
reset
polarity of RCV1 as output is active LOW, falling edge is taken when input
pin RCV1 is switched to input; default after reset
pin RCV1 is switched to output
horizontal synchronization is taken from RCV1 port (at bit SYMP = LOW) or from decoded
frame sync of “CCIR 656”input (at bit SYMP = HIGH); default after reset
horizontal synchronization is taken from RCV2 port (at bit SYMP = LOW)
defines signal type on pin RCV1; see Table 28
1
0
1
0
ORCV2
CBLF
1
PRCV1
0
1
0
1
0
ORCV1
TRCV2
1
SRCV1
DATA BYTE
AS OUTPUT
AS INPUT
FUNCTION
SRCV11
SRCV10
0
0
1
0
1
0
VS
FS
VS
FS
vertical sync each field; default after reset
frame sync (odd/even)
field sequence, vertical sync every fourth field (PAL = 0)
or eighth field (PAL = 1)
FSEQ
FSEQ
1
1
not applicable
not applicable
DATA BYTE
DESCRIPTION
HTRIG
sets the horizontal trigger phase related to signal on RCV1 or RCV2 input
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; increasing HTRIG
decreases delays of all internally generated timing signals; reference mark: analog output
horizontal sync (leading slope) coincides with active edge of RCV used for triggering at
HTRIG = 39H
相關(guān)PDF資料
PDF描述
SAA7127 Digital video encoder
SAA7127H Digital video encoder
SAA7128A Digital video encoder
SAA7128AH Digital video encoder
SAA7129AH Digital video encoder
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SAA7127 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital video encoder
SAA7127H 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital video encoder
SAA7128 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital video encoder
SAA7128A 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital video encoder
SAA7128AH 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital video encoder
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*