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參數資料
| 型號： | SAA7126H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | Digital video encoder |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP44 |
| 封裝： | 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44 |
| 文件頁數： | 14/40頁 |
| 文件大?。?/td> | 155K |
| 代理商： | SAA7126H |
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1999 May 31
14
Philips Semiconductors
Product specification
Digital video encoder
SAA7126H; SAA7127H
Table 11
Subaddresses 38H and 39H
Table 12
Subaddress 3AH
Table 13
Subaddress 54H
DATA BYTE
DESCRIPTION
GY0 to GY4
gain luminance of RGB (Cr, Y and Cb) output, ranging from (1
16
32
) to (1 +
15
32
).
Suggested nominal value =
6 (11010b), depending on external application.
gain colour difference of RGB (Cr, Y and Cb) output, ranging from (1
16
32
) to (1 +
15
32
).
Suggested nominal value =
6 (11010b), depending on external application.
GCD0 to GCD4
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
MP2C1
0
1
0
1
0
input data is twos complement from MP1 input port (encoder path)
input data is straight binary from MP1 input port; default after reset
input data is twos complement from MP2 input port (RGB path)
input data is straight binary from MP2 input port; default after reset
If VBSEN0 = 0, CVBS output signal is switched to CVBS DAC.
If VBSEN0 = 1, luminance output signal is switched to CVBS DAC; default after reset.
advanced composite sync is switched to CVBS DAC
Y, Cb and Cr for RGB dematrix is active; default after reset
Y, Cb and Cr for RGB dematrix is bypassed
horizontal and vertical trigger is taken from RCV2 and RCV1 respectively; default after reset
horizontal and vertical trigger is decoded out of “CCIR 656”compatible data at MP port
data from input ports is encoded; default after reset
colour bar with fixed colours is encoded
MP2C2
CSYNC
1
0
1
0
1
0
1
DEMOFF
SYMP
CBENB
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
EDGE1
0
1
0
1
0
MP1 data is sampled on the rising clock edge; default after reset
MP1 data is sampled on the falling clock edge
MP2 data is sampled on the rising clock edge; default after reset
MP2 data is sampled on the falling clock edge
If SYMP = 1, horizontal and vertical trigger is decoded out of “CCIR 656”compatible data at
MP2 port; default after reset.
If SYMP = 1, horizontal and vertical trigger is decoded out of “CCIR 656”compatible data at
MP1 port.
video programming system data insertion is disabled; default after reset
video programming system data insertion in line 16 is enabled
EDGE2
CCIRS
1
VPSEN
0
1
相關PDF資料 |
PDF描述 |
|---|---|
| SAA7127 | Digital video encoder |
| SAA7127H | Digital video encoder |
| SAA7128A | Digital video encoder |
| SAA7128AH | Digital video encoder |
| SAA7129AH | Digital video encoder |
相關代理商/技術參數 |
參數描述 |
|---|---|
| SAA7127 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital video encoder |
| SAA7127H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital video encoder |
| SAA7128 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital video encoder |
| SAA7128A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital video encoder |
| SAA7128AH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital video encoder |
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