參數(shù)資料
型號: SAA7103H
廠商: NXP SEMICONDUCTORS
元件分類: 顏色信號轉(zhuǎn)換
英文描述: Circular Connector; MIL SPEC:MIL-C-5015; Body Material:Metal; Series:GT; No. of Contacts:48; Connector Shell Size:36; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight
中文描述: COLOR SIGNAL ENCODER, PQFP44
封裝: 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44
文件頁數(shù): 45/76頁
文件大?。?/td> 289K
代理商: SAA7103H
2001 Sep 25
45
Philips Semiconductors
Product specification
Digital video encoder
SAA7102; SAA7103
Table 49
Subaddress 3AH
Table 50
Subaddress 54H
Table 51
Subaddresses 55H to 59H
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
CBENB
0
1
0
data from input ports is encoded
colour bar with fixed colours is encoded
horizontal and vertical trigger is taken from FSVGC or both VSVGC and HSVGC; default
after reset
horizontal and vertical trigger is decoded out of “ITU-R BT.656”compatible data at PD port
Y-C
B
-C
R
to RGB dematrix is active; default after reset
Y-C
B
-C
R
to RGB dematrix is bypassed
pin 26 provides a horizontal sync for non-interlaced VGA components output (at PIXCLK)
pin 26 provides a composite sync for interlaced components output (at XTAL clock)
input luminance data is twos complement from PD input port
input luminance data is straight binary from PD input port; default after reset
input colour difference data is twos complement from PD input port
input colour difference data is straight binary from PD input port; default after reset
SYMP
1
0
1
0
1
0
1
0
1
DEMOFF
CSYNC
Y2C
UV2C
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
VPSEN
0
1
0
video programming system data insertion is disabled; default after reset
video programming system data insertion in line 16 is enabled
If SYMP = 1, horizontal and vertical trigger is decoded out of “ITU-R BT.656”compatible
data at MP2 port; default after reset.
If SYMP = 1, horizontal and vertical trigger is decoded out of “ITU-R BT.656”compatible
data at MP1 port.
internal PPD2 data is sampled on the rising clock edge
internal PPD2 data is sampled on the falling clock edge; see Tables 25 to 29; default after
reset
internal PPD1 data is sampled on the rising clock edge; see Tables 25 to 29; default after
reset
internal PPD1 data is sampled on the falling clock edge
CCIRS
1
EDGE2
0
1
EDGE1
0
1
DATA BYTE
DESCRIPTION
REMARKS
VPS5
VPS11
VPS12
VPS13
VPS14
fifth byte of video programming system data
eleventh byte of video programming system data
twelfth byte of video programming system data
thirteenth byte of video programming system data
fourteenth byte of video programming system data
in line 16; LSB first; all other bytes are not
relevant for VPS
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