參數(shù)資料
型號(hào)： SAA6750
廠商： NXP Semiconductors N.V.
英文描述： Encoder for MPEG2 image recording EMPIRE
中文描述： 為MPEG2編碼器帝國(guó)的形象記錄
文件頁(yè)數(shù)： 19/60頁(yè)
文件大小： 217K
代理商： SAA6750
2000 May 03
19
Philips Semiconductors
Product specification
Encoder for MPEG2 image recording
(EMPIRE)
SAA6750H
7.3.3.4
Sync processing
Becausethesynchronizationinformationmaybedelivered
by a video data source in two different ways, the internal
sync processing of the SAA6750H is carried out in two
related modes:
1.
The ITU-T 656 mode:
The ITU-T 656 recommendation describes the
unidirectional interconnection between a video data
source and a video data sink. Luminance and
chrominance data as well as the complete set of
control data (V-sync, H-sync, field indication or byte
information such as SAV, EAV, etc.) are transferred
interleaved on one 8-bit bus. Both, sync and data
signal, are in the form of binary coded 8-bit words.
The external sync signals HSYNC, VSYNC and FID
are not used.
2.
The external sync mode:
The synchronization may also be provided via
pins HSYNC, VSYNC and FID. In this case, the
8-bit bus carries only the video data information.
Theinternalsyncprocessingmodemaybeselectedbythe
I
2
C-bus control bit SMOD (see Tables 3 and 22).
Sync signals must be active at regular time intervals. If a
time interval is too short, a sync is skipped. Top and
bottomfieldsmustfolloweach other.Iftwotopfieldsortwo
bottom fields follow each other immediately, than the
second field is skipped.
The number of clock cycles and H-sync signals that have
to occur before processing starts (horizontal and vertical
shift) can be set via the I
2
C-bus. In this way the active part
of the video can be determined. The vertical shift can be
specified independently for top and bottom fields by using
the control words ‘Vertical shift top field’ and ‘Vertical shift
bottom field’ (see Table 22). The horizontal shift is
controlled by control word ‘Horizontal shift’. The shift can
beprogrammedinarangeof127 clockcyclesinhorizontal
direction respectively 127 lines in vertical direction.
Horizontal shift should be carried out in steps of a multiple
of 4 because a minimum data sequence (C
B
, Y, C
R
and Y)
needs 4 clock cycles. It should be noted that the horizontal
blanking in PAL mode takes 280 clock cycles and in
NTSC mode 268 cycles.
Due to the fact that the horizontal offset value can not
compensate the whole blanking interval, the polarity of the
three external sync lines (H-SYNC, V-SYNC and FID) can
also be adapted via the I
2
C-bus. Control bits HREFP,
VREFP and FIDP are used for this purpose
(see Table 22).
Internally, the edge-detection circuitries for these signals
change polarity with these settings. By this way different
synchronization schemes are supported. The horizontal
respectively vertical processing starts with the selected
edge.
Due to requirements from the internal vertical filtering the
line based processing needs 3 horizontal sync pulses
during vertical blanking which have to follow directly the
active part of the frame (e.g. 288 active lines in
PAL mode). The related line data is not processed.
This restriction does not allow edge selection at the end of
the previous field [e.g. vertical sync of line 623 or line 1
(see Fig.3)]. In this case the polarity bit VREFP has to be
set to select the falling edge of the sync lines.
The following sections contain descriptions of different
styles of synchronization signals and how they are
handled in the SAA6750H.
7.3.3.5
Sync processing PAL (50 Hz)
The PAL (50 Hz) input signal has 625 lines per frame and
typically takes 1728 clock cycles per line. The minimum
number of clock cycles per line is 1706. The active part of
a field consists of 288 lines of 720 pixels (see Fig.7).
Figures 3 and 4 and the related Table 7 give an example
illustrating how different sources providing different
external sync signals can be adapted to the SAA6750H.
In the given example, the SAA711x is connected to
pins HSYNC, VSYNC and FID and provides external sync
signals in two different modes: according to the timing
convention of the ITU-T 656 mode and in a SAA711x
proprietary format. In addition another mode HREF/VREF
is mentioned in Table 7. From a timing point of view the
HREF/VREF mode behaves like ITU-T 656, but horizontal
sync and vertical sync signals (VSYNC) are inverted. See
data sheet SAA7111A for detailed information.
As mentioned, in addition to the external sync mode, the
ITU-T 656 mode is supported. Sections 7.3.3.7, 7.3.3.8
and Figs 7 and 8 contain detailed information on this sync
mode.
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SAA6750H 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Encoder for MPEG2 image recording EMPIRE
SAA6752HS 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
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SAA6752HS/V103,557 功能描述:IC AUD/VID ENCODER MPEG 208-SQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類(lèi)型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類(lèi)型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱(chēng):Q4645799
SAA6752HS/V104 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
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