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參數(shù)資料
| 型號： | SAA569x |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Enhanced TV microcontrollers with On-Screen Display (OSD) |
| 中文描述： | 與微控制器在強(qiáng)化電視屏幕顯示（OSD） |
| 文件頁數(shù)： | 9/116頁 |
| 文件大?。?/td> | 532K |
| 代理商： | SAA569X |
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2002 May 06
9
Philips Semiconductors
Objective specification
Enhanced TV microcontrollers with
On-Screen Display (OSD)
SAA567x; SAA569x
Note
1.
A15_LN, A16_LN and A17_LN form a linear address space and may be used as an alternative to A15_BK (pin 33)
and ROMBK2 to ROMBK0 (pins 56, 57 and 58) for external program ROM access.
A15_BK
33
O
address line A15 when using ROMBK outputs for external program ROM
access
ROMBK SFR selection bits for external program ROM access >64 kbytes
ROMBK0 to
ROMBK2
RAMBK0 to
RAMBK1
INTD
58 to 56
O
51, 50
O
RAMBK SFR selection bits for external program SRAM data storage
>64 kbytes; Use A0 to A14 and A15_BK as lower address bits
interrupt disable for emulation (internal pull-up)
61
I
SYMBOL
PIN
TYPE
DESCRIPTION
7
MICROCONTROLLER
The functionality of the microcontroller used in this device
is described here with reference to the industry standard
80C51 microcontroller. A full description of its functionality
can be found in “Handbook IC20 80C51-Based 8-bit
Microcontrollers”
7.1
Microcontroller features
80C51 microcontroller core standard instruction set and
timing
0.5
μ
s machine cycle
Maximum 192 kbytes
×
8-bit Program ROM, which can
be extended to 256K with additional external ROM
Maximum of 14 kbytes
×
8-bit data and display RAM
15-level interrupt controller with individual
enable/disable and two level priority
Up to six external interrupts with programmable
detection characteristics
Three 16-bit Timer/counter registers
Watchdog timer
Auxiliary RAM page pointer
16-bit Data pointer
Idle, Standby and Power-down modes
32 general I/O lines
Eight 6-bit Pulse Width Modulator (PWM) outputs for
control of TV analog signals
One 14-bit PWM for Voltage Synthesis Tuner (VST)
control
8-bit Analog-to-Digital Converter (ADC) with four
multiplexed inputs
Two high current outputs for directly driving LEDs etc.
I
2
C-bus byte level interface with dual ports
UART for asynchronous serial communication
External ROM and SRAM compatibility.
8
MEMORY ORGANISATION
The device has the capability of a maximum of 192 kbyte
Program ROM and 14 kbyte Data RAM internally.
8.1
ROM bank switching
The 128 kbyte Program ROM variant is arranged in four
banks of 32 kbytes. One of the 32 kbyte banks is common
and is always addressable. The other three banks
(Bank 0, 1 and 2) can be selected with SFR ROMBK
bits <2:0> (see Table 2 and Fig.3).
The 192 kbyte Program ROM variant is arranged in six
banks of 32 kbytes. One of the 32 kbyte banks is common
and is always addressable. The other five banks
(Bank 0, 1, 2, 3 and 4) can be selected with SFR ROMBK
bits <2:0> (see Table 2 and Fig.3). If this variant is used
with an additional external ROM, then a further two banks
(Bank 5 and 6) can be selected with SFR ROMBK
bits <2:0> (see Table 2 and Fig.3).
Table 2
ROM bank selection
ROMBK2 ROMBK1 ROMBK0
0 to 32
kbytes
32 to 64
kbytes
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
common
common
common
common
common
common
common
reserved
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
reserved
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