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參數(shù)資料
| 型號(hào)： | SAA569x |
| 廠(chǎng)商： | NXP Semiconductors N.V. |
| 英文描述： | Enhanced TV microcontrollers with On-Screen Display (OSD) |
| 中文描述： | 與微控制器在強(qiáng)化電視屏幕顯示（OSD） |
| 文件頁(yè)數(shù)： | 38/116頁(yè) |
| 文件大小： | 532K |
| 代理商： | SAA569X |
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2002 May 06
38
Philips Semiconductors
Objective specification
Enhanced TV microcontrollers with
On-Screen Display (OSD)
SAA567x; SAA569x
10 POWER SAVING MODES OF OPERATION
Three power saving modes are incorporated in the
SAA567x; SAA569x device: Standby, Idle and
Power-down. When utilizing one of these modes, power to
the device (V
DDP
, V
DDC
and V
DDA
) should be maintained,
since power saving is achieved by clock gating on a
section-by-section basis.
10.1
Standby mode
During Standby mode, the Acquisition and Display
sections of the device are disabled. The following
functions remain active:
80C51 CPU core
Memory interface
I
2
C-bus interface
Timer/counters
Watchdog timer
UART, SAD and PWMs.
To enter Standby mode, the STANDBY bit in the
ROMBK register must be set. Once in Standby, the crystal
oscillator continues to run, but the internal clocks to
AcquisitionandDisplayaregatedout.However,theclocks
to the 80C51 CPU Core, Memory Interface, I
2
C-bus,
UART, Timer/counters, Watchdog timer and Pulse Width
Modulators are maintained. Since the output values on
RGB and VDS are maintained, the display output must be
disabled before entering this mode.
The Standby mode may be used in conjunction with both
Idle and Power-down modes. Hence, prior to entering
either Idle or Power-down, the STANDBY bit may be set,
thus allowing wake-up of the 80C51 CPU core without fully
waking the entire device. (This enables detection of a
Remote Control source in a power saving mode.)
10.2
Idle mode
During Idle mode, Acquisition, Display and the
CPU sections of the device are disabled. The following
functions remain active:
Memory interface
I
2
C-bus interface
Timer/counters
Watchdog timer
UART, SAD and PWMs.
To enter Idle mode, bit IDL in the PCON register must be
set.TheWatchdog timermustbedisabledprior toentering
Idle to prevent the device being reset.
Once in Idle mode, the crystal oscillator continues to run,
but the internal clock to the CPU, Acquisition and Display
are gated out. However, the clocks to the Memory
Interface, I
2
C-bus, Timer/counters, Watchdog timer and
Pulse Width Modulators are maintained. The CPU state is
frozen along with the status of all SFRs. Internal
RAM contentsaremaintained,asarethedeviceoutputpin
values. Since the output values on RGB and VDS are
maintained, the Display output must be disabled before
entering this mode.
There are three methods available to recover from Idle:
Assertion of an enabled interrupt will cause bit IDL to be
cleared by hardware, thus terminating Idle mode. The
interrupt is serviced and, following the instruction RETI,
the next instruction to be executed will be the one after
the instruction that put the device into Idle mode.
A second method of exiting Idle is via an interrupt
generated by the SAD DC Compare circuit. When the
SAA567x; SAA569x is configured in this mode,
detection of an analog threshold at the input to the SAD
may be used to trigger wake-up of the device i.e.
TV Front Panel Key-press. As above, the interrupt is
serviced, and following the instruction RETI, the next
instruction to be executed will be the one following the
instruction that put the device into Idle.
The third method of terminating Idle mode is with an
external hardware reset. Since the oscillator is running,
the hardware reset need only be active for 24 crystal
clocks at 12 MHz to complete the reset operation. Reset
defines all SFRs and Display memory to a pre-defined
state, but maintains all other RAM values. Code
execution commences with the Program Counter set to
‘0000’.
10.3
Power-down mode
In Power-down mode, the crystal oscillator is stopped. The
contents of all SFRs and Data memory are maintained,
however, the contents of the Auxiliary/Display memory are
lost. The port pins maintain the values defined by their
associated SFRs. Since the output values on RGB and
VDS are maintained, the Display output must be made
inactive before entering Power-down mode.
The Power-down mode is activated by setting bit PD in the
PCON register. It is advisable to disable the Watchdog
timer prior to entering Power-down. Recovery from
Power-down takes several milliseconds as the oscillator
must be given time to stabilize.
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| SAA5677HL | Enhanced TV microcontrollers with On-Screen Display (OSD) |
| SAA5700GP | Chinese Character System Teletext CCST decoder |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| SAA5700 | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Chinese Character System Teletext CCST decoder |
| SAA5700GP | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Chinese Character System Teletext CCST decoder |
| SAA5731 | 制造商:The Stanley Works 功能描述: |
| SAA5X9X | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Economy teletext and TV microcontrollers |
| SAA6579 | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Radio Data System RDS demodulator |
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