參數(shù)資料
型號: SAA5522PS
廠商: NXP Semiconductors N.V.
英文描述: Standard TV Microcontrollers with On-Screen Display(OSD)
中文描述: 微控制器與標準電視屏幕顯示(OSD)
文件頁數(shù): 20/80頁
文件大?。?/td> 340K
代理商: SAA5522PS
1999 Oct 27
20
Philips Semiconductors
Preliminary specification
Standard TV microcontrollers with
On-Screen Display (OSD)
SAA55xx
Pulse Width Modulator 5 Control Register (PWM5)
PW5E
PW5V5 to PW5V0
activate this PWM (logic 1)
pulse width modulator high time
Pulse Width Modulator 6 Control Register (PWM6)
PW6E
PW6V5 to PW6V0
activate this PWM (logic 1)
pulse width modulator high time
Pulse Width Modulator 7 Control Register (PWM7)
PW7E
PW7V5 to PW7V0
activate this PWM (logic 1)
pulse width modulator high time
ROM Bank (ROMBK)
STANDBY
standby activation bit
I
2
C-bus Slave Address Register (S1ADR)
ADR6 to ADR0
GC
I
2
C-bus slave address to which the device will respond
enable I
2
C-bus general call address (logic 1)
I
2
C-bus Control Register (S1CON)
CR2 to CR0
clock rate bits; CR<2:0>:
000 = 100 kHz bit rate
001 = 3.75 kHz bit rate
010 = 150 kHz bit rate
011 = 200 kHz bit rate
100 = 25 kHz bit rate
101 = 1.875 kHz bit rate
110 = 37.5 kHz bit rate
111 = 50 kHz bit rate
enable I
2
C-bus interface (logic 1)
START flag.
When this bit is set in slave mode, the hardware checks the I
2
C-bus
and generates a START condition if the bus is free or after the bus becomes free.
If the device operates in master mode it will generate a repeated START
condition.
STOP flag.
If this bit is set in a master mode a STOP condition is generated. A
STOP condition detected on the I
2
C-bus clears this bit. This bit may also be set
in slave mode in order to recover from an error condition. In this case no STOP
condition is generated to the I
2
C-bus, but the hardware releases the SDA and
SCL lines and switches to the not selected receiver mode. The STOP flag is
cleared by the hardware.
ENSI
STA
STO
BIT
FUNCTION
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