- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372111 > SAA5500PS (NXP Semiconductors N.V.) Standard TV microcontrollers with On-Screen Display (OSD)(帶全屏顯示的標準型TV控制器) PDF資料下載
參數(shù)資料
| 型號： | SAA5500PS |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Standard TV microcontrollers with On-Screen Display (OSD)(帶全屏顯示的標準型TV控制器) |
| 中文描述： | 微控制器與標準電視屏幕顯示（OSD）（帶全屏顯示的標準型電視控制器） |
| 文件頁數(shù)： | 38/80頁 |
| 文件大?。?/td> | 311K |
| 代理商： | SAA5500PS |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁當前第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁
1999 Oct 27
38
Philips Semiconductors
Preliminary specification
Standard TV microcontrollers with
On-Screen Display (OSD)
SAA55xx
16 I
2
C-BUS SERIAL I/O
The I
2
C-bus consists of a serial data (SDA) line and a
serial clock (SCL) line. The definition of the I
2
C-bus
protocol can be found in the document “The I
2
C-bus and
how to use it (including specification)” This document may
be ordered using the code 9398 393 40011.
The device operates in four modes:
Master transmitter
Master receiver
Slave transmitter
Slave receiver.
The microcontroller peripheral is controlled by the Serial
Control SFR (S1CON) and its status is indicated by the
Status SFR (S1STA). Information is transmitted/received
to/from the I
2
C-bus using the Data SFR (S1DAT) and the
Slave Address SFR (S1ADR) is used to configure the
slave address of the peripheral.
The byte level I
2
C-bus serial port is identical to the I
2
C-bus
serial port on the P8xCE558, except for the clock rate
selection bits CR<2:0> in S1CON. The operation of the
subsystem is described in detail in the “P8xCE558 data
sheet”
16.1
I
2
C-bus port selection
Two I
2
C-bus ports are available SCL0/SDA0 and
SCL1/SDA1. The selection of the port is done using
TXT21.I
2
C PORT 0 and TXT21.I
2
C PORT 1. When the
port is enabled, any information transmitted from the
device goes onto the enabled port. Any information
transmitted to the device can only be acted on if the port is
enabled.
If both ports are enabled then data transmitted from the
device is seen on both ports, however data transmitted to
the device on one port can not be seen on the other port.
17 MEMORY INTERFACE
The memory interface controls access to the embedded
Dynamic Random Access Memory (DRAM), refreshing of
the DRAM and page clearing. The DRAM is shared
between Data Capture, display and microcontroller
sections. The Data Capture section uses the DRAM to
store acquired information that has been requested.
The display reads from the DRAM information and
converts it into RGB values. The microcontroller uses the
DRAM as embedded auxiliary RAM.
17.1
Memory structure
The memory is partitioned into two distinct areas, the
dedicated Auxiliary RAM area, and the Display RAM area.
The Display RAM area when not being used for Data
Capture or display, can be used as an extension to the
auxiliary RAM area.
17.1.1
A
UXILIARY
RAM
The Auxiliary RAM is not initialised at power-up.
The contents of the Auxiliary RAM are maintained during
Idle mode, but are lost if Power-down mode is entered.
17.1.2
D
ISPLAY
RAM
The Display RAM is initialised on power-up to a value
of 20H throughout. The contents of the Display RAM are
maintained when entering Idle mode. If Idle mode is exited
using an interrupt then the contents are unchanged, if Idle
mode is exited using a reset then the contents are
initialised to 20H.
17.2
Memory mapping
ThededicatedAuxiliaryRAMareaoccupiesamaximumof
8 kbytes, with an address range from 0000H to 1FFFH.
The Display RAM occupies a maximum of 10 kbytes with
an address range from 2000H to 47FFH for TXT mode
(see Fig.13).
17.3
Addressing memory
The memory can be addressed by the microcontroller in
two ways, either directly using a MOVX command, or via
Special Function Registers depending on what address is
required.
The Display memory in the range 2000H to 47FFH can
either be directly accessed using the MOVX, or via the
Special Function Registers.
17.3.1
TXT D
ISPLAY MEMORY
SFR
ACCESS
The Display memory when in TXT mode (see Fig.14) is
configured as 40 columns wide by 25 rows and occupies
1K
×
8 bits of memory. There can be a maximum of
10 display pages. Using TXT15.BLOCK<3:0>, the
required display page can be selected to be written to.
The row and column within that block is selected using
TXT9.R<4:0> and TXT10.C<5:0>. The data at the
selected position can be read or written using
TXT11.D<7:0>.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA5501PS | Standard TV microcontrollers with On-Screen Display (OSD)(帶全屏顯示的標準型TV控制器) |
| SAA5502PS | Standard TV microcontrollers with On-Screen Display (OSD)(帶全屏顯示的標準型TV控制器) |
| SAA5520 | Standard TV Microcontrollers with On-Screen Display(OSD) |
| SAA5520PS | Standard TV Microcontrollers with On-Screen Display(OSD) |
| SAA5521PS | Standard TV Microcontrollers with On-Screen Display(OSD) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA5501PS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Standard TV Microcontrollers with On-Screen Display(OSD) |
| SAA5502PS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Standard TV Microcontrollers with On-Screen Display(OSD) |
| SAA5503PS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Standard TV Microcontrollers with On-Screen Display(OSD) |
| SAA5520 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Standard TV Microcontrollers with On-Screen Display(OSD) |
| SAA5520PS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Standard TV Microcontrollers with On-Screen Display(OSD) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。