參數(shù)資料
型號(hào): SAA5500PS
廠商: NXP Semiconductors N.V.
英文描述: Standard TV microcontrollers with On-Screen Display (OSD)(帶全屏顯示的標(biāo)準(zhǔn)型TV控制器)
中文描述: 微控制器與標(biāo)準(zhǔn)電視屏幕顯示(OSD)(帶全屏顯示的標(biāo)準(zhǔn)型電視控制器)
文件頁(yè)數(shù): 35/80頁(yè)
文件大小: 311K
代理商: SAA5500PS
1999 Oct 27
35
Philips Semiconductors
Preliminary specification
Standard TV microcontrollers with
On-Screen Display (OSD)
SAA55xx
13 TIMER/COUNTER
Two 16-bit timers/counters are incorporated Timer 0 and
Timer 1.Bothcanbeconfiguredtooperateaseithertimers
or event counters.
In Timer mode, the register is incremented on every
machine cycle. It is therefore counting machine cycles.
Since the machine cycle consists of twelve oscillator
periods, the count rate is
1
12
f
osc
= 1 MHz.
In Counter mode, the register is incremented in response
toanegativetransitionatitscorrespondingexternalpin T0
or T1. Since the pins T0 and T1 are sampled once per
machine cycle, it takes two machine cycles to recognise a
transition, this gives a maximum count rate of
1
24
f
osc
= 0.5 MHz.
There are six Special Function Registers used to control
the timers/counters. These are: TCON, TMOD, TL0, TH0,
TL1 and TH1.
Thetimer/counterfunctionisselectedbycontrolbits C/Tin
the Timer Mode SFR (TMOD). These two Timer/Counters
have four operating modes, which are selected by bit-pairs
(M1 and M0) in TMOD. Detail of the modes of operation is
given in “Handbook IC20, 80C51-Based 8-bit
Microcontrollers”
TL0 and TH0 are the actual Timer/Counter registers for
Timer 0. TL0 is the low byte and TH0 is the high byte.
TL1 and TH1 are the actual Timer/Counter registers for
Timer 1. TL1 is the low byte and TH1 is the high byte.
14 WATCHDOG TIMER
The Watchdog Timer is a counter that once in an overflow
state forces the microcontroller into a reset condition.
The purpose of the Watchdog Timer is to reset the
microcontroller if it enters an erroneous processor state
(possibly caused by electrical noise or RFI) within a
reasonable period of time. When enabled, the Watchdog
circuitry will generate a system reset if the user program
failstoreloadtheWatchdogTimerwithinaspecifiedlength
of time known as the Watchdog Interval (WI).
The Watchdog Timer consists of an 8-bit counter with an
11-bit prescaler. The prescaler is fed with a signal whose
frequency is
1
12
f
osc
(1 MHz for 12 MHz oscillator).
The 8-bit timer is incremented every ‘t’ seconds where:
14.1
Watchdog Timer operation
The Watchdog operation is activated when the WLE bit in
the Power Control SFR (PCON) is set. The Watchdog can
be disabled by software by loading the value 55H into the
Watchdog Key SFR (WDTKEY). This must be performed
before entering Idle or Power-down mode to prevent
exiting the mode prematurely.
Once activated the Watchdog Timer SFR (WDT) must be
reloaded before the timer overflows. The WLE bit must be
set to enable loading of the WDT SFR, once loaded the
WLE bit is reset by hardware, this is to prevent erroneous
software from loading the WDT SFR.
The value loaded into the WDT defines the Watchdog
Interval (WI).
The range of intervals is from WDT = 00H which gives
524 ms to WDT = FFH which gives 2.048 ms.
15 PULSE WIDTH MODULATORS
The device has eight 6-bit Pulse Width Modulated (PWM)
outputs for analog control of e.g. volume, balance, bass,
treble, brightness, contrast, hue and saturation. The PWM
outputs generate pulse patterns with a repetition rate of
21.33
μ
s, with the high time equal to the PWM SFR value
multiplied by 0.33
μ
s. The analog value is determined by
the ratio of the high time to the repetition time, a DC
voltage proportional to the PWM setting is obtained by
means of an external integration network (low-pass filter).
15.1
PWM control
The relevant PWM is enabled by setting the PWM enable
bitPWxE in the PWMx Control Register (wherex = 0 to 7).
The high time is defined by the value PWxV<5:0>.
t
12
2048
1
osc
f
12
2048
1
×
12
10
6
---------------------
2.048 ms
=
×
×
=
×
×
=
WI
256
WDT
(
)
t
×
256
WDT
(
)
2.048 ms
×
=
=
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