2005 Mar 09
19
Philips Semiconductors
Product specification
Multi page intelligent teletext decoder
SAA5360; SAA5361
Notes
1.
2.
3.
4.
Periphery current is dependent on external components and voltage levels on I/Os.
V
TN
is the drop across a protection transistor which clamps the input to V
DD
. The maximum value is V
TN
= 0.75 V
Crystal order number 4322 143 05561.
If the 4322 143 05561 crystal is not used, the formula in the crystal specification should be used. The mean of the
capacitances due to the chip at XTALIN and at XTALOUT is C
IO
, where C
IO
= 7 pF. C
ext
is a value for the mean of
the stray capacitances due to the external circuits at XTALIN and XTALOUT.
a) C
osc(typ)
= 2C
L
C
IO
C
ext
. Capacitor C
osc
may need to be reduced from the initial selected value.
b) C
O(max)
= 35
0.5 (C
osc
+ C
IO
+ C
ext
) pF. The maximum value for the crystal holder capacitance is to ensure
start-up.
A device must internally provide a hold time of at least 300 ns for the SDA signal, referenced to the V
IH(min)
of the
SCL signal, in order to bridge the undefined region of the falling edge of SCL.
The maximum t
HD;DAT
has only to be met if the device does not stretch the LOW period of the SCL signal (t
LOW(SCL)
).
A fast mode I
2
C-bus device can be used in a standard-mode I
2
C-bus system, but the requirement t
SU;DAT
≥
250 ns
must be met. This requirement is met for a device that does not stretch t
LOW(SCL)
. If a device does stretch t
LOW(SCL)
,
the next data bit to the SDA line must be output t
r(max)
+ t
SU;DAT
= 1000 + 250 = 1250 ns before the SCL line is
released (according to the standard-mode I
2
C-bus specification).
C
b
= total capacitance of one bus line in pF.
5.
6.
7.
8.
12 APPLICATION INFORMATION
12.1
EMC guidelines
Optimization of circuit return paths and minimization of
common mode emission is achieved by a double sided
Printed-Circuit Board (PCB) with low inductance ground
plane.
On a single-sided PCB a local ground plane under the
whole IC should be present. Preferably, the PCB local
ground plane connection should not be connected to other
grounds on route to the PCB ground. Do not use wire links.
Wire links cause ground inductance which increases
ground bounce.
The supply pins can be decoupled at the ground pin plane
below the IC. This is easily achieved by using surface
mount capacitors, which, at high frequency, are more
effective than components with leads.
Using a device socket would increase the area and
therefore increase the inductance of the external bypass
loop.
To provide a high-impedance to any high frequency
signals on the V
DD
supplies to the IC, a ferrite bead or
inductor can be connected in series with the supply line
close to the decoupling capacitor. To prevent signal
radiation, pull-up resistors of signal outputs should not be
connected to the V
DD
supply on the IC side of the ferrite
bead or inductor.
OSCGND should only be connected to the crystal load
capacitors and not to any other ground connection.
Distances to physical connections of associated active
devices should be as short as possible.
PCB output tracks should have close proximity, mutually
coupled and ground return paths.