參數(shù)資料
型號(hào): SAA5284
廠(chǎng)商: NXP Semiconductors N.V.
英文描述: Multimedia video data acquisition circuit
中文描述: 多媒體視頻數(shù)據(jù)采集電路
文件頁(yè)數(shù): 4/24頁(yè)
文件大?。?/td> 159K
代理商: SAA5284
1998 Feb 05
4
Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
SAA5284
5
MAIN FUNCTIONAL BLOCKS
1.
2.
3.
4.
5.
6.
Input clamp and sync separator
Analog-to-digital converter
Multi-standard data slicer and clock regenerator
Packet filtering; (8 and 4) Hamming correction
On-chip data cache
Line selectable data type
7.
8.
9.
10. Multi-standard parallel interface
11. I
2
C-bus interface
12. Power-on reset.
12, 13.5, 15 and 16 MHz clock or oscillator options
FIFO access to data
Interrupt and DMA support
Figure 1 shows a block diagram of the SAA5284.
6
BLOCK DIAGRAM
Fig.1 Block diagram.
handbook, full pagewidth
MGG740
ANALOG
SWITCH
SAA5284
MULTI-STANDARD
HOST INTERFACE
I
2
C-BUS
INTERFACE
400 kHz
SLAVE
FIFO
PACKET BUFFER AND
FRONT END CONTROL
REGISTERS
PACKET
FILTERING (e.g.
WST packets
30/31)
ANALOG
VIDEO TO
DATA BYTE
CONVERTER
(DATA
DEMODULATOR)
OSCILLATOR
AND TIMING
OSCOUT
OSCGND
OSCIN
PACKET BUFFER RAM
2 kbyte
(45 packets)
35
44
31
32
10
33
34
42
43
2
39
38
36
37
11
3
SDA
SCL
4
5
30 to 28
20 to 27
WR
(1)
16
15
14
VDDAVSSAVDDXVDDDVSSD3
RESET
17
6
41
40
1
VPOIN0
HREF
VPOIN1
LLC
LLC2
RD
(1)
DMACK
(1)
DMARQ
CVBS0
CVBS1
VSSD1
VSSD2
data path
control
13
12
7
8
9
18
19
IREF
BLACK
8
3
D7 to D0
(1)
A2 to A0
(1)
RDY
(1)
SEL1
SEL0
INT
CS1
DENB
CS0
(1) Multi-functional pins, see Chapter 7.
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