參數(shù)資料
型號(hào)： SAA4994H
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： Field and line rate converter with noise reduction
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝： 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, MS-022, SOT-322-2, QFP-160
文件頁(yè)數(shù)： 12/40頁(yè)
文件大小： 147K
代理商： SAA4994H
2001 Nov 23
12
Philips Semiconductors
Product specification
Field and line rate converter
with noise reduction
SAA4994H
7
FUNCTIONAL DESCRIPTION
The FAL (fal_top) module builds the functional top level of
the SAA4994H. It connects the luminance data path, the
chrominance data path and the luminance
(de)compression with SAA4994H inputs and outputs as
well as controlling logic. Outside of fal_top there are only
the pad cells, boundary scan test cells, the boundary scan
test controller, the clock tree, the test enable tree and the
input port registers.
Figure 4 shows a simplified block diagram of fal_top
module. It displays the flow of pixel data (solid lines) and
controls (broken lines) between the modules inside.
Basic functionality of the modules in fal_top module is as
follows:
KER (kernel): Y (luminance) data path
COL (colour): UV (chrominance) data path
YDP (Y-DPCM): compression (and decompression) of
luminance output (and input) data by Differential Pulse
Code Modulation (DPCM)
LSE (line sequencer): generate line frequent control
signals
SNE (interface): Synchronous No parity Eight bit
Reception and Transmission (SNERT) interface to a
microcontroller.
The SNERT interface operates in a slave receive and
transmit mode for communication with a microcontroller,
which resides on peripheral circuits (e.g. SAA4978H)
together with a SNERT master. The SNERT interface
transforms serial data from the microprocessor (via the
SNERT bus) into parallel data to be written into the
SAA4994Hs write registers and parallel data from
SAA4994Hs read registers into serial data to be sent to the
microcontroller. The SNERT bus consists of 3 signals:
1.
SNCL: used as serial clock signal, generated by the
master
2.
SNDA: used as bidirectional data line
3.
SNRST: used as a reset signal, generated by the
microcontroller to indicate the start of a transmission.
The processing of a video field begins on the rising edge
of the RE_F input signal. As indicated in Fig.4, the
SAA4994H receives its inputs and generates its outputs at
the following clock cycles after RE_F (see Table 1).
Table 1
Clock cycle references
There is an algorithmic delay of 3 lines between input and
output data. Therefore, the main data output on the
F and G bus begins while the fourth input line is read.
Writing to the B and D bus starts one input line later. The
readandwriteenablesignalsRE_A,WE_BandRE_Ccan
be shifted by control registers REaShift, WEbdShift and
REceShift, which are implemented in the line sequencer.
The fal_top module itself reads the following control
register bits (addresses):
NrofFMs (017H)
MatrixOn (026H) and BusGControl (028H)
MemComp and MemDecom (026H).
NrofFMs, MatrixOn and BusGControl are used to enable
the D and G output bus, respectively. MemComp and
MemDecom are connected to YDP to control luminance
data compression and decompression. These control
register signals are not displayed in Fig.4. Further
information on the control registers is given in Chapter 8.
SIGNAL
LATENCY
RE_F
RE_C
YC and UVC
RE_A
YA and UVA
YF, YG, UVF
and UVG
WE_B
YB and UVB
0
62 cycles + REceShift
63 cycles
93 cycles + REaShift
94 cycles
147 cycles + 3 input lines
159 cycles + 4 input lines + WEbdShift
159 cycles + 4 input lines
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