- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372109 > SAA4993H (NXP SEMICONDUCTORS) Field and line rate converter with noise reduction PDF資料下載
參數(shù)資料
| 型號： | SAA4993H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Field and line rate converter with noise reduction |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, MS-022, SOT-322-2, QFP-160 |
| 文件頁數(shù)： | 12/40頁 |
| 文件大?。?/td> | 148K |
| 代理商： | SAA4993H |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當(dāng)前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
2001 Nov 23
12
Philips Semiconductors
Product specification
Field and line rate converter
with noise reduction
SAA4993H
7
FUNCTIONAL DESCRIPTION
The fal_top module builds the functional top level of the
SAA4993H. It connects the luminance data path, the
chrominance data path and the luminance
(de)compression with SAA4993H inputs and outputs as
well as controlling logic. Outside of the fal_top module,
there are only the pad cells, boundary scan test cells, the
boundary scan test controller, the clock tree, the test
enable tree and the input port registers.
Figure 4 shows a simplified block diagram of the fal_top
module. It displays the flow of pixel data (solid lines) and
controls (broken lines) between the modules inside.
Basic functionality of the modules in the fal_top module is
as follows:
KER (kernel): Y (luminance) data path
COL (colour): UV (chrominance) data path
YDP (Y-DPCM): compression (and decompression) of
luminance output (and input) data by Differential Pulse
Code Modulation (DPCM)
LSE (line sequencer): generate line frequent control
signals
SNE (interface): Synchronous No parity Eight bit
Reception and Transmission (SNERT) interface to a
microcontroller.
The SNERT interface operates in a slave receive and
transmit mode for communication with a microcontroller,
which resides on peripheral circuits (e.g. SAA4978H)
together with a SNERT master. The SNERT interface
transforms serial data from the microcontroller (via the
SNERT bus) into parallel data to be written into the
SAA4993Hs write registers and parallel data from
SAA4993Hs read registers into serial data to be sent to the
microcontroller. The SNERT bus consists of 3 signals:
1.
SNCL: used as serial clock signal, generated by the
master
2.
SNDA: used as bidirectional data line
3.
SNRST: used as a reset signal, generated by the
microcontroller to indicate the start of a transmission.
The processing of a video field begins on the rising edge
of the RE_F input signal. As indicated in Fig.4, the
SAA4993H receives its inputs and generates its outputs at
the following clock cycles after RE_F (see Table 1).
Table 1
Clock cycle references
There is an algorithmic delay of 3 lines between input and
output data. Therefore, the main data output on the
F and G bus begins while the fourth input line is read.
Writing to the B and D bus starts one input line later. The
readandwriteenablesignalsRE_A,WE_B,RE_C,WE_D
and RE_E can be shifted by control registers REaShift,
WEbdShift and REceShift, which are implemented in the
line sequencer.
The fal_top module itself reads the following control
register bits (addresses):
NrofFMs (017H)
MatrixOn (026H) and BusGControl (028H)
MemComp and MemDecom (026H).
NrofFMs, MatrixOn and BusGControl are used to enable
the D and G output bus, respectively. MemComp and
MemDecom are connected to YDP to control luminance
data compression and decompression. These control
register signals are not displayed in Fig.4. Further
information on the control registers is given in Chapter 8.
SIGNAL
LATENCY
RE_F
RE_C and
RE_E
YC, YE, UVC
and UVE
RE_A
YA and UVA
YF, YG, UVF
and UVG
WE_B and
WE_D
YB, YD, UVB
and UVD
0
62 cycles + REceShift
63 cycles
93 cycles + REaShift
94 cycles
147 cycles + 3 input lines
159 cycles + 4 input lines + WEbdShift
159 cycles + 4 input lines
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA4994H | Field and line rate converter with noise reduction |
| SAA4998H | Field and line rate converter with noise reduction and embedded memory |
| SAA5246 | 10K OHM 0.1% 1/16W CHP RES (0603) 103 |
| SAA5246A | Integrated VIP and Teletext IVT1.0 |
| SAA5246AGP | Integrated VIP and Teletext IVT1.0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA4994H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Field and line rate converter with noise reduction |
| SAA4995WP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:PANorama-IC PAN-IC |
| SAA4996H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Motion Adaptive Colour Plus And Control IC MACPACIC for PALplus |
| SAA4997H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:VErtical Reconstruction IC VERIC for PALplus |
| SAA4998H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Field and line rate converter with noise reduction and embedded memory |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。