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參數(shù)資料
| 型號： | SAA4977H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Besic |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | PLASTIC, SOT-318-2, QFP-80 |
| 文件頁數(shù)： | 8/32頁 |
| 文件大?。?/td> | 186K |
| 代理商： | SAA4977H |
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1998 Jul 23
8
Philips Semiconductors
Preliminary specification
Besic
SAA4977H
V
SSA6
YOUT
V
DDA5
78
79
80
analog ground 6
Y analog output
analog supply voltage 5 (3.3 V)
SYMBOL
PIN
DESCRIPTION
7
FUNCTIONAL DESCRIPTION
7.1
Analog-to-digital conversion
7.1.1
C
LAMP CIRCUIT
,
CLAMPING
Y
TO DIGITAL LEVEL
16
AND
UV
TO
0 (2’
S COMPLEMENT
)
A clamp circuit is applied for each input channel, to map
the colourless black level in each video line (on the sync
back porch) to level 16 for Y and to the centre level of the
converters for U and V. During the clamp period, an
internally generated clamp pulse is used to switch on the
clamp action. An operational transconductance amplifier
like construction, which references to voltage reference
points in the ladders of the ADCs, will provide a current on
the input of the YUV signals, in order to bring the signals
to the correct DC value. This current is proportional to the
DC error, but is limited to
±
100
μ
A. When the clamping
action is off, the residual clamp current should be very low
in order not to drift away within a video line.
7.1.2
G
AIN ELEMENTS FOR AUTOMATIC GAIN CONTROL
A variable amplifier is used to map the possible YUV input
range to the ADC range. A rise of 6 dB up to a drop fall of
6 dB w.r.t. the nominal values can be achieved. The gain
setting within this range is done digitally via control
registers. For this purpose a gain setting DAC is
incorporated. The smallest step in the gain setting should
be hardly visible on the picture, which can be met with
smallest steps of 0.4%/step.
Luminance and chrominance gain settings can be
separately controlled. The reason for this split is that
U and V may be gain adjusted already, whereas
luminance is to be adjusted by the SAA4977H AGC. On
the other hand, for RGB originated sources, Y, U and V
should be adjusted with the same AGC gain.
7.1.3
A
NALOG ANTI
-
ALIASING PREFILTERING
A third order linear phase filter is applied on each of the Y,
U and V channels. It provides a notch on f
CLK
(16 MHz) to
strongly prevent aliasing to low frequencies, which would
be the most disturbing. The bandwidth of the filters is
designed for
3 dB at 5.6 MHz. The filters can be
bypassed if external filtering with other characteristics is
desired.
7.1.4
T
RIPLE
8-
BIT ANALOG
-
TO
-
DIGITAL CONVERSION
Three identical ADCs are used to convert Y, U and V with
16 MHz data rate. A multi-step type ADC is applied here.
7.2
Digital processing at 1f
H
level
7.2.1
O
VERLOAD DETECTION
The overload detection provides information to make
efficient use of the AGC. The number of overflows per
video field in the luminance channel is accumulated by a
14-bit counter. The 8 MSBs of this counter can be read out
by the microprocessor respectively via the I
2
C-bus.
Overflow levels can be programmed as 216, 224,
232 and 240.
7.2.2
D
IGITAL CLAMP CORRECTION FOR
UV
During 32 samples within the clamp position the clamp
error is measured and accumulated to make a low-pass
filtered value of the clamp error. Then a vertical recursive
filter is used to further low-pass this error value. This value
can be read by the microprocessor or directly be used to
correct the clamp error. It is also possible to give a fixed
correction value by the microprocessor.
7.2.3
4 : 4 : 4
TO
4 : 1 : 1
DOWN
-
SAMPLING AND
UV
CORING
The U and V samples from the ADC are low-pass filtered,
before being subsampled with a factor of 2. Coring is
applied to the subsampled signal to obtain no gain for low
amplitudes which is considered to be noise. Coring levels
can be programmed as 0 (off),
±
1
2
,
±
1 and
±
2 LSB.
The U and V samples from the 4 : 2 : 2 data are low-pass
filtered again, before being subsampled a second time
with a factor of 2 and formatted to 4 : 1 : 1 format.
7.2.4
Y-
DELAY
The Y samples can be shifted onto 8 positions w.r.t. the
UV samples. This shift is meant to account for a possible
difference in delay previous to the SAA4977H. The zero
delay setting is suitable for the nominal case of aligned
input data according to the interface format standard.
The other settings provide four samples less delay to three
sample more delay in Y.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA4978 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Picture Improved Combined Network PICNIC |
| SAA4978H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Picture Improved Combined Network PICNIC |
| SAA4979H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Sample rate converter with embedded high quality dynamic noise reduction and expansion port |
| SAA4981 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Monolithic integrated 16 : 9 compressor |
| SAA4981T | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Monolithic integrated 16 : 9 compressor |
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