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參數(shù)資料
| 型號： | SAA4977H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Besic |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | PLASTIC, SOT-318-2, QFP-80 |
| 文件頁數(shù)： | 19/32頁 |
| 文件大小： | 186K |
| 代理商： | SAA4977H |
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1998 Jul 23
19
Philips Semiconductors
Preliminary specification
Besic
SAA4977H
Note
1.
Detailed information about the software dependent I
2
C-bus registers can be found in Application Note “I
2
C-bus
register specification of the SAA4977H”(AN98054).
8
In accordance with the Absolute Maximum Rating System (IEC 134).
LIMITING VALUES
9
THERMAL CHARACTERISTICS
39H
0 to 2
3 and 4 pk_delta
5 and 6 pk_neggain
7
0 to 3
pk_corthr
4 to 7
pk_tau
peaking tau:
1
16
(0, 1, 2, 3, 4, 5, 6, 8)
peaking amplitude dependent attenuation:
1
4
(0, 1, 2, 4)
peaking attenuation of undershoots:
1
4
(0, 1, 2, 4)
reserved
peaking coring threshold 0,
±
8,
±
16 to
±
120 LSB
reserved
3AH
Subaddress 3BH and 3CH (sidepanels overlay)
3BH
0 to 3
4 to 7
0 to 7
overlay_u
overlay_v
overlay_y
sidepanels overlay U (4 MSB)
sidepanels overlay V (4 MSB)
sidepanels overlay Y (8 MSB)
3CH
Subaddress 3DH to 3FH (sidepanel position)
3DH
3EH
3FH
0 to 7
0 to 7
0 and 1 sidepanel_fdel
2
output_range
sidepanel_start sidepanel start position (8 MSB) w.r.t. the rising edge of HRD signal
sidepanel_stop
sidepanel stop position (8 MSB) w.r.t. the rising edge of HRD signal
fine delay of sidepanel signal in LLD clock cycles: 0, 1, 2 and 3
output range (output range = 0: 9 bit for the nominal output signal,
black level: 288 and white level: 767; output range = 1: 10 bit for the nominal
output signal, black level 64 and white level 1023)
uv_inv
inverts UV input signals: 0 = no inversion, 1 = inversion
ydelay_out
variable Y-delay in LLD clock cycles:
7,
6,
5,
4,
3,
2,
1 and 0
reserved
3
4 to 6
7
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
V
DDA(1,2,3)
V
DDD(1,2,3)
V
DDA(4,5)
V
DDD(4,5,6)
V
DDIO
V
i
T
stg
T
amb
analog supply voltage front-end
digital supply voltage front-end
analog supply voltage back-end
digital supply voltage back-end
digital I/O supply voltage back-end
input voltage for all I/O pins
storage temperature
operating ambient temperature
0.5
0.5
0.5
0.5
0.5
0.5
20
20
+5.25
+5.25
+3.45
+3.45
+5.25
+5.25
+150
+60
V
V
V
V
V
V
°
C
°
C
SYMBOL
PARAMETER
CONDITIONS
VALUE
UNIT
R
th(j-a)
thermal resistance from junction to ambient
in free air
50
K/W
ADDRESS
BIT
NAME
DESCRIPTION
相關PDF資料 |
PDF描述 |
|---|---|
| SAA4978 | Picture Improved Combined Network PICNIC |
| SAA4978H | Picture Improved Combined Network PICNIC |
| SAA4979H | Sample rate converter with embedded high quality dynamic noise reduction and expansion port |
| SAA4981 | Monolithic integrated 16 : 9 compressor |
| SAA4981T | Monolithic integrated 16 : 9 compressor |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SAA4978 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Picture Improved Combined Network PICNIC |
| SAA4978H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Picture Improved Combined Network PICNIC |
| SAA4979H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Sample rate converter with embedded high quality dynamic noise reduction and expansion port |
| SAA4981 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Monolithic integrated 16 : 9 compressor |
| SAA4981T | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Monolithic integrated 16 : 9 compressor |
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