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參數(shù)資料
| 型號： | SAA4974H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Besic without ADC |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 文件頁數(shù)： | 13/28頁 |
| 文件大小： | 173K |
| 代理商： | SAA4974H |
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1998 Apr 21
13
Philips Semiconductors
Product specification
Besic without ADC
SAA4974H
built in, that can be addressed as internal AUXRAM via
MOVX type of instruction.
7.3.1
I
2
C-
BUS
The I
2
C-bus interface in the SAA4974H is used in a slave
receive and transmit mode for communication with in
general a central system microprocessor.
The standardized bus frequencies of both 100 kHz and
400 kHz can be dealt with.
The I
2
C-bus slave address of the SAA4974H is
0 1 1 0 1 0 0 R/W.
For a detailed description of the transmission protocol
refer to brochure“I
2
C-bus and how to use t”(order number
9398 393 40011) and to Application Note “I
2
C-bus register
specification of the SAA4974H”(AN97042).
7.3.2
SNERT-
BUS
A SNERT interface is built in, which operates in a master
receive and transmit mode for communication with
peripheral circuits as SAA4990H or SAA4991WP.
The SNERT interface replaces the standard UART
interface. In contrary to the 8051 UART interface there are
additional special function registers and there is no byte
separation time between address and data.
The SNERT interface transforms the parallel data from the
microprocessor into 1 Mbaud SNERT data.
The SNERT-bus consists of three signals: SNCL used as
serial clock signal, generated by the SNERT interface;
SNDA used as bidirectional data line, and SNRST used as
reset signal, generated by the microprocessor to indicate
the start of a transmission.
The read or write operation must be set by the
microprocessor. In case of writing to the bus, 2 bytes are
loaded by the microprocessor: one for the address, the
other for the data. In case of reading from the bus, one
byte is loaded by the microprocessor for the address, the
received byte is the data from the addressed SNERT
location.
7.3.3
I/O-
PORTS
A parallel 8-bit I/O-port (P1) is available, where P1.0 is
used as SNERT reset signal (SNRST), P1.1 to P1.5 can
be used for application specific control signals, and
P1.6 and P1.7 are used as I
2
C-bus signals (SCL and
SDA).
7.3.4
W
ATCHDOG TIMER
The microprocessor contains an internal Watchdog timer,
which can be activated by setting the corresponding
special function register PCON.4. Only a synchronous
reset will clear this bit. To prevent a system reset the
watchdog timer must be reloaded in time. The Watchdog
timer is incremented every 0.75 ms. The time interval
between the timer’s reloading and the occurrence of a
reset depends on the reloaded 8-bit value.
7.4
Memory controller
The memory controller provides all necessary acquisition
clock related write signals (WE and RSTW) and display
clock related read signals (RE and IE2) to control one or
two-field memory concepts. Furthermore the drive signals
(HDFL and VDFL) for the horizontal and vertical deflection
power stages are generated. Also a horizontal blanking
pulse BLND is generated which can be used for peripheral
circuits as SAA4990H. The memory controller is
connected to the microprocessor via the host interface.
Start and stop values for all pulses, referring to the
corresponding horizontal or vertical reference signal, are
programmable under control of the internal software.
To allow an user access to these control signals via
I
2
C-bus a range of subaddresses is reserved; for a
detailed description of this user interface refer to
Application Note “I
2
C-bus register specification of the
SAA4974H”(AN97042).
7.4.1
WE
The write enable signal for field memory 1 is a composite
signal consisting of a horizontal and a vertical part.
The horizontal position with reference to the rising edge of
the HA signal and the vertical position with reference to the
rising edge of the VA signal are programmable.
7.4.2
RSTW
Reset write signal for field memory 1; this signal is derived
from the positive edge of the VA input signal and has a
pulse width of 64
μ
s.
7.4.3
RE
The read enable signal for field memory 1 is a composite
signal consisting of a horizontal and a vertical part.
The horizontal position with reference to the rising edge of
the HA signal and the vertical position with reference to the
rising edge of the VA signal are programmable.
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