參數(shù)資料
型號: SAA4974
廠商: NXP Semiconductors N.V.
英文描述: Besic without ADC
中文描述: 貝西奇沒有模數(shù)轉換器
文件頁數(shù): 18/28頁
文件大?。?/td> 173K
代理商: SAA4974
1998 Apr 21
18
Philips Semiconductors
Product specification
Besic without ADC
SAA4974H
Digital output signals: WE and RSTW (C
L
= 15 pF); timing referred to SWC clock
V
OH
V
OL
t
d(o)
t
h(o)
HIGH-level output voltage
LOW-level output voltage
output delay time
output hold time
I
OH
=
2.0 mA
I
OL
= 1.6 mA
see Fig.11
see Fig.11
2.4
4
0.4
20
V
V
ns
ns
Digital output signal: SWC (C
L
= 15 pF); timing referred to LLA clock
V
OH
V
OL
t
d(o)
HIGH-level output voltage
LOW-level output voltage
output delay time
I
OH
=
2.0 mA
I
OL
= 1.6 mA
see Fig.11
2.4
3
0.4
12
V
V
ns
Digital output signals: IE2, BLND, RE, HDFL and VDFL (C
L
= 15 pF); timing referred to LLD clock
I
OH
=
2.0 mA
V
OL
LOW-level output voltage
I
OL
= 1.6 mA
t
d(o)
output delay time
see Fig.11
t
h(o)
output hold time
see Fig.11
V
OH
HIGH-level output voltage
2.4
4
0.4
20
V
V
ns
ns
Digital output signal: HRD
V
OH
V
OL
HIGH-level output voltage
LOW-level output voltage
I
OH
=
2.0 mA
I
OL
= 1.6 mA
2.4
0.4
V
V
Digital input/output signals: P1.1 to P1.5 and SNRST
V
OH
V
OL
V
IH
V
IL
HIGH-level output voltage
LOW-level output voltage
HIGH-level input voltage
LOW-level input voltage
I
OH
=
0.06 mA
I
OL
= 1.6 mA
2.4
0
2.0
0
0.45
5.5
0.8
V
V
V
V
Digital input signals: YI and UVI; timing referred to LLD clock
V
IH
V
IL
t
su(i)
t
h(i)
HIGH-level input voltage
LOW-level input voltage
input set-up time
input hold time
2.0
4
3
5.5
0.8
V
V
ns
ns
see Fig.11
see Fig.11
Digital input signal: HA; timing referred to LLA clock
V
IH
V
IL
t
su(i)
t
h(i)
HIGH-level input voltage
LOW-level input voltage
input set-up time
input hold time
2.0
7
4
5.5
0.8
V
V
ns
ns
see Fig.11
see Fig.11
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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