參數(shù)資料
型號(hào)： SAA4974
廠商： NXP Semiconductors N.V.
英文描述： Besic without ADC
中文描述： 貝西奇沒(méi)有模數(shù)轉(zhuǎn)換器
文件頁(yè)數(shù)： 14/28頁(yè)
文件大小： 173K
代理商： SAA4974
1998 Apr 21
14
Philips Semiconductors
Product specification
Besic without ADC
SAA4974H
7.4.4
IE2
Input enable signal for field memory 2, can be directly set
or reset by the microprocessor.
7.4.5
HDFL
Horizontal deflection signal for driving an deflection circuit;
this signal has a cycle time of 32
μ
s and a pulse width of
76 LLD clock cycles.
7.4.6
VDFL
Vertical deflection signal for driving a deflection circuit; this
signal has a cycle time of 10 ms; start and stop value with
reference to the rising edge of the VA signal is
programmable in steps of 16
μ
s.
7.4.7
BLND
Horizontal blanking signal for peripheral circuits e.g.
SAA4990H, start and stop values with reference to the
rising edge of HRD are programmable.
7.5
Clock and sync interfacing
The line locked acquisition clock LLA and the line locked
display clock LLD must be provided by the application.
Also an acquisition clock synchronous line frequent signal
must be provided by the application at pin HA. A vertical
50 or 60 Hz synchronization signal has to be applied on
pin VA.
Typically the circuit operates as a two clock system, i.e.
LLA has to be supplied with a 16 MHz clock and LLD with
a 32 MHz clock. The circuit can also operate as a one
clock system, i.e. a 32 MHz line locked display clock has
to be provided to both pins LLA and LLD. In this case the
internal horizontal pixel counter is reset by the rising edge
of the HA input, and the corresponding control signal
en_hdsp_rst has to be set via the I
2
C-bus.
A display clock synchronous line frequent signal is put out
at pin HRD providing a duty factor of 50%. The rising edge
of HRD is also the reference for display related control
signals as BLND, RE, HDAV and HBDA.
The acquisition clock is buffered internally and put out as
serial write clock (SWC) for supplying the field memory.
7.6
4 : 1 : 1 digital input interfacing
Digital input bus format
The start position, when the first phase of the 4 : 1 : 1 YUV
dataword is expected on the input bus, can be defined by
the internal control signal HDAV. The luminance input
signal is expected in 8-bit straight binary format, whereas
U and V input signals are expected in twos complement
format. U and V input signals are inverted if the
corresponding control bit uv_inv is set via the I
2
C-bus.
7.7
Test mode operation
The SAA4974H provides a test mode function which
should be avoided to be entered by the customer. If the
TRST input is driven to HIGH, different test modes can be
selected by applying HIGH to the TMS input for a defined
number of LLD clock cycles. Also the ANATEST input is
only active during test mode operation. To exit the test
mode TMS and TRST must be driven LOW.
4 : 1 : 1 FORMAT
INPUT
PIN
Y07
Y06
Y05
Y04
Y03
Y02
Y01
Y00
U07
U06
V07
V06
Y17
Y16
Y15
Y14
Y13
Y12
Y11
Y10
U05
U04
V05
V04
Y27
Y26
Y25
Y24
Y23
Y22
Y21
Y20
U03
U02
V03
V02
Y37
Y36
Y35
Y34
Y33
Y32
Y31
Y30
U01
U00
V01
V00
YI7
YI6
YI5
YI4
YI3
YI2
YI1
YI0
UVI7
UVI6
UVI5
UVI4
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PDF描述
SAA4974H Besic without ADC
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參數(shù)描述
SAA4974H 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Besic without ADC
SAA4977H 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Besic
SAA4978 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Picture Improved Combined Network PICNIC
SAA4978H 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Picture Improved Combined Network PICNIC
SAA4979H 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Sample rate converter with embedded high quality dynamic noise reduction and expansion port
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